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  order number: 245052-001 82443MX pciset   processor host bus support optimized for the intel ? pentium ? ii and mobile celeron? processors at 66 mhz gtl+ bus driver technology   integrated dram support 8 mb to 256 mb using 16-/64- /128-mb technology standard and registered sdram (synchronous) dram support (x-1-1-1 access at 66 mhz) enhanced open page arbitration sdram paging scheme   pci bus interface pci rev. 2.2, 3.3v, 33 mhz interface compliant  integrated ide controller 1 channel support for ultra dma/33 synchronous dma mode  system peripheral support enhanced dma controller support for dual cascaded 82c37 controllers interrupt controller based on two 82c59 for up to 15 interrupts system timer based on 82c54 real time clock w/ 256 bytes battery-backed ram x-bus support for sio, kbcx and flash  usb ac97 link controller  ac97 audio and modem codec interface support usb 1.1 port for serial transfers at 12 or 1.5 mbits/sec supports uhci design guide  smbus support  power management logic support for power-on suspend, suspend-to-sdram, and suspend-to-disk support for thermal alarm full support for acpi revision 1.0 specification  31 gpio pins  1.65 w tdp  492 ubga package the intel? 82443MX pciset integrates the traditional north bridge and south bridge into one device reducing power and board space for intel? pentium? ii and mobile celeron? processor-based designs. the intel 82443MX pciset may contain design defects or errors know as errata which may cause the product to deviate from published specifications. current characterized errata are available upon request.
information in this document is provided in connection with intel products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by the sale of intel products. except as provided in intel's terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties relating to fitness for a par ticular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving or life sustaining applications. intel retains the right to make changes to specifications and product descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined. int el reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising fro m future changes to them. contact your local sales office or your distributor to obtain the latest specifications before placing your product order. mobile celeron? (micro-pga and bga) processors may contain design defects or errors known as errata, which may cause the product to deviate from published specifications. current characterized errata are available upon request. copies of documents that have an ordering number and are referenced in this document, or other intel literature, may be obtained by calling 1-800-548-4725 or by visiting intels web site at http://www.intel.com . copyright ? intel corporation 1999. i 2 c is a two-wire communications bus/protocol developed by philips. smbus is a subset of the i 2 c bus/protocol and was developed by intel. implementations of the i 2 c bus/protocol or the smbus bus/protocol may require licenses from various entities, including philips electronics n.v. and north american philips corporation. * third party brands and names are the property of their respective owners.
82443MX pciset iii contents page 1. introduction ............................................................................................................................... ....... 1 1.1 82440mx chipset feature summary ............................................................................................. .1 1.2 82440mx chipset features .................................................................................................... ........ 2 2. architecture overview ................................................................................................................. 5 3. references ................................................................................................................... ...................... 6 4. signal description and pin states............................................................................................ .7 4.1 pin list .................................................................................................................... ....................... 7 4.1.1 signal description........................................................................................................ ..... 8 4.1.2 power and ground pins .................................................................................................. 22 4.2 gpio definition............................................................................................................. ................ 23 4.3 power rail overview ......................................................................................................... ........... 26 4.4 power-up state initial value ................................................................................................ ......... 27 4.5 power-on reset pin values ................................................................................................... ...... 27 4.6 power-up/reset strap options................................................................................................ ..... 35 4.7 cpu reset ................................................................................................................... ................ 37 5. power planes................................................................................................................. .................. 38 5.1 overview .................................................................................................................... .................. 38 5.2 rtc power plane ............................................................................................................. ............ 38 5.3 resume power plane .......................................................................................................... ......... 38 6. system a ddress map..................................................................................................................... .40 6.1 addressable memory support .................................................................................................. .... 40 6.2 memory map.................................................................................................................. ............... 40 6.2.1 compatibility area........................................................................................................ ... 42 6.2.1.1 dos area (00000h-9fffh; 0 - 640 kb) .................................................... 43 6.2.1.2 video buffer area (a0000h-bffffh; 640 - 768 kb).................................. 43 6.2.1.3 expansion area (c0000h-dffffh; 768 - 896 kb) .................................... 43 6.2.1.4 extended system bios area (e0000h-effffh; 896 - 960 kb)................ 43 6.2.1.5 system bios area (f0000h-fffffh; 960 kb - 1 mb).............................. 43 6.2.2 extended memory area .................................................................................................. 43 6.2.2.1 main dram address range (0010_0000h to top of main memory) ......... 44 6.2.2.2 extended smram address range (top of main memory - tseg_sz to top of main memory) ................................................................................ 44
82443MX pciset iv 6.2.2.3 pci memory address range (top of main memory to 4 gb) .................... 44 6.2.2.4 high bios area (ffc0_0000h - ffff_ffffh) ........................................ 44 6.3 system management mode (smm) memory range ..................................................................... 44 6.4 memory shadowing ............................................................................................................ .......... 45 6.5 decode rules and cross-bridge address mapping ...................................................................... 45 6.5.1 pci interface memory decode rules.............................................................................. 45 6.5.2 legacy vga range ........................................................................................................ 45 6.6 i/o address space ........................................................................................................... ............ 45 6.6.1 fixed i/o address ranges .............................................................................................. 46 6.6.2 variable i/o decode ranges .......................................................................................... 50 7. functional description ............................................................................................................... 53 7.1 mobile celeron? processor / pentium ? ii processor host interface............................................ 53 7.1.1 overview.................................................................................................................. ....... 53 7.1.2 host bus device support................................................................................................ 53 7.1.3 special cycles............................................................................................................ ..... 55 7.1.4 symmetric multiprocessor (smp) configuration.............................................................. 56 7.1.5 in-order queue pipelining .............................................................................................. 56 7.1.6 frame buffer memory support (uswc).......................................................................... 56 7.1.7 cpu sideband interface ................................................................................................. 57 7.1.7.1 a20m# ...................................................................................................... 57 7.1.7.2 ferr# / ignne# (coprocessor error)...................................................... 57 7.1.7.3 init# ......................................................................................................... 58 7.1.7.4 interrupt signals ........................................................................................ 58 7.1.7.5 nmi ........................................................................................................... 58 7.1.7.6 smi# ......................................................................................................... 58 7.1.7.7 stpclk#.................................................................................................. 58 7.2 memory interface............................................................................................................ .............. 59 7.2.1 dram interface ............................................................................................................ .. 59 7.2.1.1 dram interface overview......................................................................... 59 7.2.2 dram organization and configuration ........................................................................... 59 7.2.2.1 configuration mechanism for dimms ........................................................ 61 7.2.3 sdram cycle encoding ................................................................................................. 63 7.2.4 dram address translation and decoding...................................................................... 68 7.2.5 sdramc register programming.................................................................................... 69 7.2.6 sdram paging policy .................................................................................................... 70 7.2.6.1 overview................................................................................................... 70 7.2.6.2 open page arbitration policies.................................................................. 70
82443MX pciset v 7.2.6.3 selective auto precharge policy ............................................................... 70 7.2.7 dram power throttling .................................................................................................. 71 7.2.7.1 overview................................................................................................... 71 7.2.7.2 conceptual description of power throttling............................................... 71 7.2.7.3 sdram power throttling setting sequence ............................................. 72 7.2.8 sdram performance description................................................................................... 73 7.2.9 sdram optimizations .................................................................................................... 73 7.2.9.1 dual and quad bank support.................................................................... 73 7.3 system memory management .................................................................................................... .. 73 7.3.1 smram range overview ................................................................................................. 73 7.3.2 compatible smram (c_smram) .................................................................................. 74 7.3.3 extended smram (e_smram) ..................................................................................... 74 7.4 ac97 audio and modem controller............................................................................................ .. 77 7.4.1 ac97 audio controller.................................................................................................... 77 7.4.2 ac97 modem controller................................................................................................ 78 7.4.3 ac97 overview ............................................................................................................ .. 78 7.4.4 system initialization ..................................................................................................... ... 80 7.4.5 clocking.................................................................................................................. ........ 80 7.4.6 digital interface......................................................................................................... ...... 80 7.4.6.1 multi-point aclink..................................................................................... 80 7.4.6.2 ac-link digital serial interface protocol..................................................... 81 7.5 pci interface ............................................................................................................... ................. 82 7.5.1 pci interface overview ................................................................................................... 8 2 7.5.2 north bridge/cluster functionality................................................................................... 83 7.5.2.1 north bridge/cluster as a pci target ........................................................ 83 7.5.2.2 north bridge/cluster as a pci initiator....................................................... 84 7.5.2.3 delayed transactions ............................................................................... 86 7.5.3 south bridge/cluster functionality .................................................................................. 87 7.5.3.1 south bridge/cluster as a pci target ....................................................... 87 7.5.3.2 south bridge/cluster as a pci initiator...................................................... 88 7.6 dma controller .............................................................................................................. ............... 89 7.6.1 register description...................................................................................................... .. 89 7.6.2 functional description .................................................................................................... 89 7.6.2.1 dma transfer modes ................................................................................ 90 7.6.2.2 dma transfer types ................................................................................. 91 7.6.2.3 dma timings ............................................................................................ 92 7.6.2.4 x-bus / dma arbitration ............................................................................ 92 7.6.2.5 register functionality................................................................................ 94
82443MX pciset vi 7.6.2.6 software commands................................................................................. 96 7.6.2.7 terminal count summary ......................................................................... 96 7.6.2.8 x-bus refresh cycles ............................................................................... 97 7.7 pci dma ..................................................................................................................... ................. 97 7.7.1 overview.................................................................................................................. ....... 97 7.7.1.1 pc/pci dma ............................................................................................. 97 7.7.1.2 distributed dma ........................................................................................ 98 7.7.2 configuration ............................................................................................................. ..... 98 7.7.3 pc/pci.................................................................................................................... ........ 98 7.7.3.1 overview................................................................................................... 98 7.7.3.2 additional configuration ............................................................................ 98 7.7.3.3 pc/pci expansion protocol ...................................................................... 98 7.7.3.4 pc/pci expansion cycles....................................................................... 100 7.7.4 dstributed dma ............................................................................................................ 101 7.7.4.1 overview................................................................................................. 101 7.7.4.2 additional configuration .......................................................................... 101 7.7.4.3 read/write cycle protocols .................................................................... 102 7.7.4.4 calculating the i/o address..................................................................... 106 7.7.4.5 power management implications ............................................................ 108 7.7.4.6 other clarifications.................................................................................. 108 7.8 timer ....................................................................................................................... ................... 108 7.8.1 counter/timers ............................................................................................................ . 108 7.8.1.1 counter 0, system timer ........................................................................ 109 7.8.1.2 counter 1, refresh request signal ......................................................... 109 7.8.1.3 counter 2, speaker tone ........................................................................ 109 7.8.2 interval timer address map .......................................................................................... 109 7.8.3 programming the interval timer.................................................................................... 110 7.8.3.1 write operations ..................................................................................... 111 7.8.3.2 interval timer control word format ........................................................ 111 7.8.3.3 counter latch command ........................................................................ 112 7.9 rtc......................................................................................................................... ................... 113 7.9.1 rtc overview .............................................................................................................. 113 7.9.2 rtc registers and ram............................................................................................... 114 7.9.3 rtc update cycle ........................................................................................................ 11 4 7.9.4 rtc interrupts ............................................................................................................ .. 114 7.9.5 lockable ram ranges ................................................................................................. 115 7.9.6 rtc external connections............................................................................................ 115 7.9.6.1 rtc crystal ............................................................................................ 115
82443MX pciset vii 7.9.6.2 rtc battery ............................................................................................ 115 7.9.7 century rollover .......................................................................................................... . 115 7.10 interrupt controller....................................................................................................... ............... 115 7.10.1 interrupt controller functional description .................................................................... 116 7.10.1.1 interrupt sequence.................................................................................. 118 7.10.1.2 interrupt acknowledge cycle................................................................... 119 7.10.1.3 programming the interrupt controller ...................................................... 120 7.10.1.4 end-of-interrupt operation....................................................................... 123 7.10.1.5 register functionality.............................................................................. 126 7.10.1.6 interrupt masks ....................................................................................... 127 7.10.1.7 reading the interrupt controller status ................................................... 127 7.10.1.8 interrupt steering .................................................................................... 128 7.10.2 serial irq scheme ....................................................................................................... 1 30 7.10.2.1 overview................................................................................................. 130 7.10.2.2 protocol................................................................................................... 130 7.10.2.3 smi# via serirq................................................................................... 132 7.10.2.4 serirq oring with isa irq.................................................................. 132 7.11 usb host controller ........................................................................................................ ........... 132 7.12 ide interface .............................................................................................................. ................ 133 7.12.1 ata register block decode.......................................................................................... 134 7.12.2 pio ide transactions ................................................................................................... 13 6 7.12.3 pio ide timing modes ................................................................................................. 136 7.12.4 enhanced timing modes .............................................................................................. 138 7.12.4.1 piordy masking.................................................................................... 139 7.12.4.2 pio 32-bit ide data port accesses ........................................................ 139 7.12.4.3 pio ide data port prefetching and posting ............................................ 139 7.12.5 bus master function..................................................................................................... 1 39 7.12.5.1 physical region descriptor format ......................................................... 139 7.12.5.2 operation ................................................................................................ 140 7.12.6 ultra dma/33 synchronous dma operation ............................................................... 141 7.12.6.1 signal descriptions ................................................................................. 141 7.12.6.2 operation ................................................................................................ 142 7.12.6.3 crc calculation ...................................................................................... 142 7.12.6.4 reference ............................................................................................... 142 7.13 x-bus ...................................................................................................................... .................... 143 7.13.1 target i/o interface..................................................................................................... .. 143 7.13.2 x-bus clock (sysclk) generation............................................................................... 144 7.13.3 wait state and shortened cycle generation................................................................. 144
82443MX pciset viii 7.13.4 i/o recovery............................................................................................................. .... 145 7.14 system management bus (smbus)............................................................................................ 14 5 7.14.1 smbus host interface................................................................................................... 14 5 7.14.2 smbus slave interface ................................................................................................. 147 7.15 gpio ....................................................................................................................... ................... 147 7.15.1 configuration ............................................................................................................ .... 147 7.16 system clocking............................................................................................................ ............. 148 8. pinout and package information ........................................................................................... 150 8.1 82440mx pinout .............................................................................................................. ........... 150 8.2 82440mx package dimensions .................................................................................................. 151
82443MX pciset ix list of figures page figure 1. 82440mx platform block diagram....................................................................................... .............. 5 figure 2. platform power rails ................................................................................................. ...................... 26 figure 3. memory address map ................................................................................................... .................. 41 figure 4. pci configuration space block diagram ................................................................................ ......... 52 figure 5. coprocessor error timing diagram ..................................................................................... ............ 58 figure 6. dimm configuration with fet switches................................................................................. .......... 61 figure 7. smram mapping ........................................................................................................ .................... 76 figure 8. ac97 controller connection to its companion codec................................................................... .. 79 figure 9. 440mx-based ac97 audio system....................................................................................... .......... 79 figure 10. ac97 standard bi-directional audio frame........................................................................... ........ 82 figure 11. 440mx pci bus topology .............................................................................................. ............... 83 figure 12. internal dma controller ............................................................................................. .................... 90 figure 13. x-bus arbiter with dma in fixed priority (2-way rotation) ........................................................... ... 93 figure 14. x-bus arbiter with dma in rotating priority ......................................................................... .......... 94 figure 15. dma serial channel passing protocol................................................................................. .......... 99 figure 16. interrupt controller block diagram.................................................................................. ............. 117 figure 17. initialization sequence for the 440mx icw modes of operation.................................................. 122 figure 18. automatic rotation mode example..................................................................................... ......... 124 figure 19. polled mode ......................................................................................................... ....................... 125 figure 20. section of interrupt steering logic (without serial irq) ............................................................... 129 figure 21. usb system conceptual view.......................................................................................... ........... 133 figure 22. enhanced ide timing mode components ................................................................................. .. 137 figure 23. inserting wait states by de-asserting piordy ........................................................................ ... 137 figure 24. physical region descriptor table entry.............................................................................. ......... 140 figure 25. isa 8-bit i/o cycles ................................................................................................ ..................... 144 figure 26. 440mx smbus interfaces .............................................................................................. .............. 146 figure 27. system clocking..................................................................................................... ..................... 148 figure 28. 82440mx pinout (top side view) ...................................................................................... .......... 150 figure 29. 82440mx pinout (pin side view)...................................................................................... ........... 151 figure 30. 82440mx bga package dimensions (top and side view) ......................................................... 152 figure 31. 82440mx bga package dimensions (bottom view) ................................................................... 153
82443MX pciset x list of tables page table 1. main feature set ...................................................................................................... .......................... 1 table 2. host interface signal description..................................................................................... ................... 8 table 3. memory i/f signal description......................................................................................... ................. 11 table 4. ide signal description................................................................................................ ...................... 12 table 5. other system/test signal description .................................................................................. ............ 13 table 6. pci i/f signal description............................................................................................ ..................... 13 table 7. ac97 signal description ............................................................................................. .................... 15 table 8. interrupt signal description.......................................................................................... ..................... 16 table 9. rtc signal description................................................................................................ ..................... 16 table 10. clocks, reset, plls and miscellaneous signal description............................................................ 16 table 11. usb signal description............................................................................................... .................... 17 table 12. smbus signal description ............................................................................................. ................. 17 table 13. power management signal description .................................................................................. ........ 17 table 14. gpio signal description .............................................................................................. ................... 19 table 15. x-bus signal description............................................................................................. .................... 19 table 16. core power pins...................................................................................................... ....................... 22 table 17. host i/f power pins .................................................................................................. ...................... 22 table 18. rtc power pins ....................................................................................................... ...................... 23 table 19. usb power pins ....................................................................................................... ...................... 23 table 20. resume power pins .................................................................................................... ................... 23 table 21. vref power pins ...................................................................................................... ..................... 23 table 22. gpio pins programmed through config. dev.7, fn. 0.................................................................... 23 table 23. system resume with gpio signals programmed as functional pins ............................................ 25 table 24. power-on reset values by signal group ................................................................................ ....... 27 table 25. dram interface signals............................................................................................... ................... 33 table 26. miscellaneous signals ................................................................................................ .................... 34 table 27. power-up options during reset ........................................................................................ ............. 36 table 28. mobile celeron? processor / pentium ? ii processor frequency ratios ........................................ 37 table 29. power planes ......................................................................................................... ........................ 38 table 30. rtc well signals..................................................................................................... ....................... 38 table 31. resume well signals.................................................................................................. .................... 39 table 32. memory segment attributes ............................................................................................ ............... 41 table 33. compatibility memory area............................................................................................ ................. 42 table 34. fixed i/o ranges decoded by the 440mx ................................................................................ ...... 46 table 35. variable i/o decode ranges (available i/o space is 0 - 64kb)...................................................... 51
82443MX pciset xi table 36. host bus transactions supported ...................................................................................... ............ 53 table 37. host bus responses supported ......................................................................................... ............ 54 table 38. special cycle transactions........................................................................................... .................. 55 table 39. events causing init# active .......................................................................................... ................ 58 table 40. sample of possible options for 6 row/3 dimm configurations ...................................................... 60 table 41. data bytes on dimm used for programming dram registers ....................................................... 62 table 42. command truth table .................................................................................................. .................. 63 table 43. dqm truth table ...................................................................................................... ...................... 64 table 44. operative command table .............................................................................................. ............... 64 table 45. ma muxing vs. dram address split..................................................................................... .......... 69 table 46. programmable sdram timing parameters................................................................................. ... 70 table 47. available memory for smram when extended smram enabled................................................... 74 table 48. extended smram dram memory regions ................................................................................... 75 table 49. smram range decode................................................................................................... ............... 77 table 50. smram decode control................................................................................................. ................ 77 table 51. ac97 audio pin description.......................................................................................... ................. 79 table 52. supported data streams ............................................................................................... ................. 81 table 53. pci commands supported by the north bridge/cluster when acting as a pci target.................... 83 table 54. pci commands supported by north bridge/cluster when acting as a pci initiator ........................ 85 table 55. pci commands supported by the south bridge/cluster when acting as a pci target ................... 87 table 56. pci commands supported by the south bridge/cluster when acting as a pci initiator.................. 88 table 57. rotating priority example ............................................................................................ ................... 94 table 58. dma transfer size .................................................................................................... ..................... 95 table 59. address shifting in 16-bit i/o dma transfers ......................................................................... ........ 95 table 60. terminal count summary ............................................................................................... ................ 97 table 61. dma cycle vs. i/o address ............................................................................................ .............. 100 table 62. pci data bus vs. dma i/o port size ................................................................................... ......... 101 table 63. dma i/o cycle width vs. be[3:0]#..................................................................................... ........... 101 table 64. 8237 registers and ddma function..................................................................................... ........ 103 table 65. mapping the 8237 register to ddma peripheral......................................................................... .. 106 table 66. interval timer functions ............................................................................................. .................. 109 table 67. interval timer counters i/o address map.............................................................................. ....... 109 table 68. counter operating modes.............................................................................................. ............... 111 table 69. interrupt controller register i/o port address map................................................................... .... 118 table 70. typical interrupt functions.......................................................................................... .................. 118 table 71. content of interrupt vector byte for 80x86 system mode ............................................................. 12 0 table 72. suggested default values for icw registers........................................................................... ..... 121 table 73. sirq frames.......................................................................................................... ...................... 131
82443MX pciset xii table 74. ide legacy i/o ports: command block registers (cs1x# chip select) ...................................... 134 table 75. ide legacy i/o port definition: control block registers (cs3x# chip select) ............................. 134 table 76. command strobe width for ide transaction types...................................................................... 1 37 table 77. idetimx timing modes for drives 0 and 1 .............................................................................. ..... 138 table 78. ultra dma/33 control signal redefinition ............................................................................. ........ 141 table 79. system clocking...................................................................................................... ..................... 149 table 80. 82440mx package dimensions ........................................................................................... ......... 154 table 81. alphabetical bga pin list ............................................................................................ ................. 155 table 82. gpio pin list........................................................................................................ ........................ 161
82443MX pciset 1 1. introduction the intel ? 82443MX pciset (440mx) is a single-component mobile chipset that is optimized for intel ? mobile celeron? processors and pentium ? ii processors for new value and mini notebook platforms. the 440mx reduces the number of mobile chipset components without requiring any major programming model changes. it accomplishes this by integrating the 443bx north bridge chipset (without agp) and the piix4e south bridge chipset while adding a two-channel, digital ac97 link feature. this single-component mobile chipset is specifically designed to reduce system cost, space and power. the 440mx is packaged in 492 mbga (the same package as the 443bx). this document is intended for architects, engineers, product planners and marketing groups who develop technologies, products or positioning for the notebook pc market segment. 1.1 440mx feature summary table 1 summarizes the main feature set of the 440mx. table 1. main feature set features 440mx processor interface processor/host bus support 1 mobile celeron processor / pentium ii processor at 66 mhz integrated dram controller capacity 8-256 mb dimms 2 dimms (4 rows memory) data path size 64-bit without ecc type supported sdram, 66 mhz pci bus interface revision rev. 2.2 voltage 3.3v (5v tolerant buffers) pci bus masters 4 pci interrupts 4 pc-pci channels 1 miscellaneous bus audio: ac'97 2 channels ide 1 channel
82443MX pciset 2 features 440mx i/o components super i/o (fdc, pp, sp, ir), optional rtc external (on x-bus only) interface support for kbc, flash, and other slow devices x-bus (8-bit) power management functions acpi 1.0 compliant power management yes legacy power management support yes system management support smbus yes wired for management (wfm) yes miscellaneous general purpose input/output 31 gpios programmable chip selects 2 (muxed w/gpio) for x-bus option usb 2 ports / 1 hci 1.2 440mx features  processor/host bus support  optimized for mobile celeron processors or pentium ii processors at 66 mhz host bus frequency  supports 32-bit mobile celeron processor / pentium ii processor bus addressing (no support for processor host bus 36-bit address extension)  4 or 1 deep in-order queue; 4 or 1 deep request queue  supports uni-processor systems only  in-order transaction and dynamic deferred transaction support  gtl+ bus driver technology (gated gtl+ receivers for reduced power)  integrated dram controller  8 mb to 256 mb using 16/64/128 mb generation  supports up to 2 double-sided dimms (4 rows memory)  64-bit data interface without ecc  66 mhz memory clock  standard and registered sdram (synchronous) dram support (x-1-1-1 access)  command issue rate of one per clock  supports only 3.3v dimm dram configurations  support for 16-/64-/128- mbit dram devices  support for symmetrical and asymmetrical dram addressing  support for x8, x16 and x32 dram device width
82443MX pciset 3  refresh mechanism  supports cas-before-ras  self refresh during c3, pos and suspend mode (str)  enhanced open page arbitration sdram paging scheme  support for dimm serial presence detect scheme via smbus interface  support for dram power throttling  pci bus interface  pci rev. 2.2, 3.3v, 33 mhz interface compliant  asynchronous coupling to the host bus/core frequency  pci parity generation support  cpu-to-pci write assembly of full/partial line writes  combines back-to-back sequential cpu-to-pci memory writes into pci burst writes  data streaming support from pci to dram (~120 mb/s for writes, ~100mb/s for reads)  delayed transaction support for pci reads which cannot be serviced immediately  supports concurrent cpu, pci transactions to main memory  integrated pci arbiter with multi-transaction arbitration mechanism  4 pci bus masters support for combination of graphic, lan, cardbus, audio, modem  overall arbitration scheme and concurrency  distributed arbitration model for optimum concurrency support  concurrent operations of cpu, pci supported via dedicated arbitration and data buffering logic  pci arbiter  cpu bus arbiter  dram arbitration for managing multiple request queues  internal dram controller arbitration between data requests and refresh requests  overall data buffering  distributed data buffering model for optimum concurrency  dram write buffer with read-around-write capability  dedicated cpu-dram, pci-dram read buffers  cpu-pci deferred transaction buffering (bi-directional for reads and writes)  delayed transaction read buffering for pci path  system peripherals  interrupt controller  15 interrupts with dual cascaded 8259  serial interrupt input  system timer, speaker tone generator  dma controller supports the following:  dual cascaded 8237  ddma
82443MX pciset 4  one channel pc/pci  real time clock  acpi-compliant one-month alarm  256 bytes battery-backed ram  ac97 link controller (2 channels)  interface to ac97 audio codec  interface to modem codec  gpio pins (31)  1 channel bus master ide support ata33  x-bus support  sio, kbc, and flash are x-bus based  smbus  host interface and slave interface  power management functions  acpi 1.0 compliant power management  acpi arbiter disable  pci clockrun# and pme# support  static clock gating for ac97 and usb  processor system bus power management  stop grant and halt special cycle translation from the host to the pci bus  support for system suspend/resume via susclk/sus_stat# (i.e., dram and power-on suspend)  sdram self-refresh power-down support via cke pin in suspend mode  independent, internal dynamic clock gating reduces the 440mxs average power dissipation  static stop clock support  power-on suspend mode  suspend-to-dram  suspend-to-disk  system management  smi# generation  smram space remapping to a0000h (128 kb)  optional extended smram space above 128mb, additional 128k/256k/512k/1mb tseg from top of memory, cacheable (cacheability controlled by the processor)  signals/packaging/power  416 signals  492 mbga  3.3v core and mixed 3.3v with 5v tolerant and gtl i/o buffers  1.65 w tdp (typical) power dissipation with low power features enabled
82443MX pciset 5 2. architecture overview the 440mx is a single-component chipset that integrates the north bridge and the south bridge, and an additional ac97 digital link (2 channels) into one chip. it replaces the isa interface with an 8-bit x-bus that supports kbc, sio and flash memory. figure 1 illustrates a block diagram of the 440mx platform. sio s y stem memor y (sdram) dimm#1 graphic controller crt lcd panel clock gen. ide drive (2) ac'97 codec fdc intel mobile celeron tm processor / pentium tm ii processor keyboard & ps/2 sp pp ir power management gpio smbus pci 2.2 (3.3v, 32 bit, 33 mhz) cardbus controller s y stem memor y (sdram) dimm#0 66 mhz 3.3v 3.3v, 2 chn. usb (2 ports) 66 mhz, gtl processor i/f 8-bit x- bus ide controller (1 chn.) ac'97 link (2 chn.) gpio usb (1 hci) central unit & memory controller sm controller (1 chn.) power mana g ement control bus controller flash north brid g e/ cluster south brid g e/ cluster figure 1. 440mx platform block diagram
82443MX pciset 6 3. references intel ? 82443MX pciset electrical and thermal specification, rev. 3.1 (order number) gtl+ i/o specification (order number) design for testability 82c54 datasheet (order number) serialized irq support for pci systems, rev 6.0 (order number) universal host controller interface (uhci) design guide, rev 1.1 (order number 297650-002) at attachment specification (order number) ata synchronous dma transfer protocol (proposal), rev 0.40 , quantum corp. system management bus specification, rev 1.0 pci 3.3 signaling environment dc and ac specifications ac97 rev 2.0 specification (draft rev. 0.96) pci local bus specification, revision 2.2.
82443MX pciset 7 4. signal description and pin states 4.1 pin list this section provides a detailed description of the 440mx signals. the signals are arranged in functional groups according to their associated interface. table 2 through table 15 provide pin descriptions for each signal. the state of each 440mx signal during reset is provided in the power-up state initial value section (section 0). some signals, i.e., hclkin, cpu sideband signals are voltage dependent on the cpu clock interface. for mobile celeron processors, it is 2.5v. note that the processor address and data bus signals are logically inverted. in other words, the actual values are inverted of what appears on the processor bus. all processor control signals follow normal convention. a 0 indicates an active level (low voltage) if the signal is followed by the # symbol and a 1 indicates an active level (high voltage) if the signal has no # suffix. the # symbol at the end of a signal name indicates that the active, or asserted state occurs when the signal is at a low voltage level. when # does not follow the signal name the signal is asserted at the high voltage level. the following notations are used to describe the signal type: i input pin o output pin od open drain output pin. this pin requires a pullup to the vcc of the processor core. i/od input / open drain output pin. this pin requires a pullup to the vcc of the processor core. i/o bi-directional input/output pin the signal description also includes the type of buffer used for the particular signal: gtl+ open drain gtl+ interface signal. refer to the gtl+ i/o specification for complete details. pci pci bus interface signals. these signals are compliant with the pci 5.0v signaling environment dc and ac specifications. cmos the cmos buffers are low voltage ttl compatible signals. these are 3.3v only.
82443MX pciset 8 4.1.1 signal description table 2. host interface signal description signal type description a20gate i address 20 gate . this input from the keyboard controller is logically combined with a bit in port 92h which is then output via the a20m# signal. a20gate saves the external or gate needed with various other chipsets. a20m# od address 20 mask . a20m# goes active by either setting the appropriate bit in the port 92h register, or by the a20gate input signal. ads# i/o address strobe . the processor bus owner asserts ads# to indicate the first of two cycles of a request phase. bnr# i/o block next request . used to block the current request bus owner from issuing a new request. this signal is used to dynamically control the processor bus pipeline depth. bpri# i/o priority agent bus request . the 440mx is the only priority agent on the processor bus. the 440mx asserts this signal to obtain the ownership of the address bus. this signal has priority over symmetric bus requests and will cause the current symmetric owner to stop issuing new transactions unless the hlock# signal was asserted. breq0# i/o symmetric agent bus request . breq0# is asserted during cpurst# to configure the symmetric bus agents and is negated two host clo cks after cpurst# is negated. cpurst# i/o cpu reset . the cpurst# pin is an output from the 440mx. the 440mx generates this signal based on the pcirst# signal (generated internally from the south bridge/cluster) and the sus_stat# pin. cpurst# allows the processor to begin execution in a known state. dbsy# i/o data bus busy . used by the data bus owner to hold the data bus for transfers requiring more than one cycle. defer# i/o defer . the 440mx generates a deferred response as defined by the 440mxs dynamic defer policy. the 440mx also uses the defer# signal to indicate a processor retry response. drdy# i/o data ready . asserted for each cycle that data is transferred. ferr# i numeric coprocessor error . this signal is tied to the coprocessor error signal on the processor. if ferr# is asserted, the 440mx generates an internal irq13 to its interrupt controller unit. it is also used to gate the ignne# signal to ensure that ignne# is not asserted to the processor unless ferr# is active. ha[31:3]# i/o address bus . ha[31:3]# connects to the processor address bus. during processor cycles the ha[31:3]# are inputs. note that the address bus is inverted on the processor bus. hd[63:0]# i/o host data . these signals are connected to the processor data bus. note that the data signals are inverted on the processor bus.
82443MX pciset 9 signal type description hit# i/o hit . indicates that a caching agent holds an unmodified version of the requested line. also driven in conjunction with hitm# by the target to extend the snoop window. hitm# i/o hit modified . indicates that a caching agent holds a modified version of the requested line and that this agent assumes responsibility for providing the line. also, driven in conjunction with hit# to extend the snoop window. hlock# i/o host lock . all processor cycles sampled with the assertion of hlock# and ads#, until the negation of hlock# must be atomic, i.e., no pci snoopable access to dram is allowed when hlock# is asserted by the processor. hreq(4:0)# i/o request command . asserted during both clocks of a r equest phase. in the first clock, the signals define the transaction type to a level of detail that is sufficient to begin a snoop request. in the second clock, the signals carry additional information to define the complete transaction type. the transactions supported by the 440mx host bridge are defined in section 7.1. htrdy# i/o host target ready . indicates that the target of the processor transaction is ready to enter the data transfer phase. ignne# od ignore numeric error . this signal is connected to the ignore error pin on the processor. ignne# is only used if the 440mx coprocessor error reporting function is enabled in the xbcsa register (bit 5=1). if ferr# is active, indicating a coprocessor error, a write to the coprocessor error register (f0h) causes the ignne# to be asserted. ignne# remains asserted until ferr# is negated. if ferr# is not asserted when the coprocessor error register is written, the ignne# signal is not asserted. init# od initialization. init# is asserted in response to any one of the following conditions:  when the system reset bit in the reset control register is reset to 0 and the reset cpu bit toggles from 0 to 1, the 440mx initiates a soft reset by asserting init#.  if a shut down special cycle is decoded on the pci bus.  if the rcin# signal is asserted.  if a write occurs to port 92h, bit 0. when asserted, init# remains asserted for approximately 64 pci clo cks before being negated. mobile celeron processor / pentium ii processor: during reset: high after reset: high during pos: high intr od cpu interrupt. intr is driven by the 440mx to signal the cpu that an interrupt request is pending and needs to be serviced. it is asynchronous with respect to sysclk or pciclk and is always an output. the interrupt controller must be programmed following pcirst# to ensure that intr is at a known state. during reset: low after reset: low during pos: low
82443MX pciset 10 signal type description nmi od non-maskable interrupt . nmi is used to force a non-maskable interrupt to the processor. the 440mx can generate an nmi when either serr# or iochk# is asserted. the processor detects an nmi on a rising edge. nmi is reset by setting the corresponding nmi source enable/disable bit in the nmi status and control register. rcin# i keyboard controller reset processor . this pin from the keyboard controller saves the external or gate needed. this is called reset processor, because it uses the kbc terminology. however, the signal is mainly used to generate init#. rs(2:0)# i/o response . indicates type of response according to the following: rs[2:0] response type 000 idle state 001 retry response 010 deferred response 011 reserved (not driven by the 440mx) 100 hard failure (not driven by the 440mx) 101 no data response 110 implicit writeback 111 normal data response smi# od system management interrupt . smi# is an active low output synchronous to pciclk that is asserted by the 440mx in response to one of many enabled hardware or software events. note : the 440mx allows synchronous smi events to generate smi# even after stpclk# has occurred. stpclk# od stop clock request . stpclk# is an active low synchronous output synchronous to pciclk that is asserted by the 440mx in response to one of many hardware or software events. when the processor samples stpclk# asserted, it responds by stopping its internal clock.
82443MX pciset 11 table 3. memory i/f signal description signal type description cke(3:0)# o clock enable (sdram) . clock enable is used to signal a self-refresh or power- down command to an sdram array when entering system suspend. cke is also used to dynamically power down inactive sdram rows. cs(3:0)# o chip select (sdram). for memory rows configured with sdram these pins select the particular sdram components during the active state. dqm(7:0) o input/output data mask (sdram). these pins act as synchronized output enables during read cycles and as a byte enables during write cycles. the read cycles require tdqz clock latency before the functions are performed. in the case of write cycles, byte-masking functions are performed during the same clock when write data is driven (i.e., 0 clock latency). ma(13,12#,11# , 10, (9:0)#) o memory address (sdram). ma(13,12#:11#,10,(9:0)#) signals provide the multiplexed row and column address to dram. each memory address line has a programmable buffer strength to optimize for different signal loading conditions. md(63:0) i/o memory data (sdram). these signals interface to the dram data bus. scas# o sdram column address strobe (sdram). the scas# signal generates sdram commands encoded on sras#/scas#/we# signals. sras# o sdram row address strobe (sdram). the sras# signal generates sdram commands encoded on sras#/scas#/we# signals. we# o write enable signal (sdram). we# is asserted during writes to dram. the we# lines have a programmable buffer strength that can be optimized for different signal loading conditions.
82443MX pciset 12 table 4. ide signal description signal type description pda[2:0] o ide device address . these output signals are connected to the corresponding signals on the ide connectors. they are used to indicate which byte in either the ata command block or control block is being addressed. pdcs1# o ide device chip selects for 100 range . for ata command register block. this output signal is connected to the corresponding signal on the ide connector. pdcs3# o ide device chip select for 300 range . for ata control register block. this output signal is connected to the corresponding signal on the ide connector. pdd[15:0] i/o ide device data . these signals directly drive the corresponding signals on the ide connector. pddak# o ide device dma acknowledge . this signal directly drives the dak# signal on the ide connectors. it is asserted by the 440mx to indicate to ide dma slave devices that a given data transfer cycle (assertion of pdior# or pdiow#) is a dma data transfer cycle. this signal is used in conjunction with the pci bus master ide function and is not associated with any at-compatible dma channel. pddrq i ide device dma request . this input signal is directly driven from the dreq signal on the ide connector. it is asserted by the ide device to request a data transfer. this signal is used in conjunction with the pci bus master ide function and is not associated with any at-compatible dma channel. pdior# (pdwstb / prdmardy#) o disk i/o read (pio and non-ultra33 dma) . this is the command to the ide device that it may drive data onto the pdd lines. data is latched by the 440mx on the de-assertion edge of pdior#. the ide device is selected either by the ata register file chip selects (pdcs1#, pdcs3#) and the pda lines, or the ide dma acknowledge (pddak#). disk write strobe (ultra33 dma writes to disk). this is the data write strobe for writes to disk. when writing to disk, the 440mx drives valid data on rising and falling edges of pdwstb. disk dma ready (ultra33 dma reads from disk). this is the dma ready for reads from disk. when reading from disk, the 440mx de-asserts prdmardy# to pause burst data transfers. pdiow# (pdstop) o disk i/o write (pio and non-ultra33 dma) . this is the command to the ide device that it may latch data from the pdd lines. the ide device latches data on the de-assertion edge of pdiow#. the ide device is selected either by the ata register file chip selects (pdcs1#, pdcs3#) and the pda lines, or the ide dma acknowledge (pddak#). disk stop (ultra33 dma). the 440mx asserts this signal to terminate a burst. piordy i i/o channel ready (pio) . this signal keeps the strobe active (pdior# on reads, pdiow# on writes) longer than the minimum width. it adds wait states to pio transfers. disk read strobe (ultra33 dma reads from disk). when reading from disk, the 440mx latches data on rising and falling edges of this signal.
82443MX pciset 13 signal type description disk dma ready (ultra33 dma writes to disk). when writing to disk, this signal is de-asserted by the disk to pause burst data transfers. table 5. other system/test signal description signal type description spkr / gpio(14) o / i/o speaker . the spkr signal is the output of counter 2 and is internally "anded" with port 61h bit 1 to provide speaker data enable. this signal drives an external speaker driver device. upon pcirst#, its output state is 0. this signal is muxed with gpio(14). refer to section 4.2 for the pin count. test# i intel reserved signal. this signal must be strapped to an external pull-up resistor. table 6. pci i/f signal description signal type description ad[31:0] i/o pci address/data . ad[31:0] is a multiplexed address and data bus. during the first clock of a transaction, ad[31:0] contain a physical byte address (32 bits). during subsequent clo cks, ad[31:0] contain data. c/be[3:0]# i/o bus command and byte enables . the command and byte enable signals are multiplexed on the same pci pins. during the address phase of a transaction, c/be[3:0]# define the bus command. during the data phase c/be[3:0]# are used as byte enables. c/be[3:0]# command type 0 0 0 0 interrupt acknowledge 0 0 0 1 special cycle 0 0 1 0 i/o read 0 0 1 1 i/o write 0 1 1 0 memory read 0 1 1 1 memory write 1 0 1 0 configuration read 1 0 1 1 configuration write 1 1 0 0 memory read multiple 1 1 1 0 memory read line 1 1 1 1 memory write and invalidate all command encodings not shown here are reserved. the 440mx does not use reserved values, and does not respond if a pci master generates a cycle using one of the reserved values. clkrun# i/od pci clock run . clkrun# uses a protocol between the 440mx and various peripherals for dynamic starting and stopping of the pci clock.
82443MX pciset 14 signal type description devsel# i/o device select . the 440mx asserts devsel# to claim a pci transaction. as an output, the 440mx asserts devsel# when it claims a pci cycle. as an input, devsel# indicates the response to a the 440mx-initiated transaction on the pci bus. devsel# is three-stated from the leading edge of pcirst# and remains three-stated by the 440mx until driven as a target. frame# i/o cycle frame . frame# is driven by the current initiator to indicate the beginning and duration of an access. while frame# is asserted data transfers continue. when frame# is negated the transaction is in the final data phase. frame# is an input to the 440mx when it is the target. frame# is an output when the 440mx is the initiator and remains three-stated by the 440mx until driven as an initiator. gnta# / gpio(3) o / io pc/pci dma acknowledge . see section 7.7 for a description. if the pc/pci request is not needed, these can be used as general-purpose inputs. irdy# i/o initiator ready . irdy# indicates the 440mx's ability, as an initiator, to complete the current data phase of the transaction. it is used in conjunction with trdy#. a data phase is completed on any clock when both irdy# and trdy# are sampled asserted. during a write, irdy# indicates the 440mx has valid data present on ad[31:0]. during a read, it indicates the 440mx is prepared to latch data. irdy# is an input to the 440mx when the 440mx is the target and an output when the 440mx is an initiator. irdy# remains three-stated by the 440mx until driven as an initiator. par i/o calculated parity . par is "even" parity and is calculated on 36 bits ad[31:0] plus c/be[3:0]#. "even" parity means that the number of "1"s within the 36 bits plus par is counted and the sum is always even. par is always calculated on 36 bits regardless of the valid byte enables. par is generated for address and data phases and is only guaranteed to be valid one pci clock after the corresponding address or data phase. par is driven and three-stated identically to the ad[31:0] lines except that par is delayed by exactly one pci clock. par is an output during the address phase (delayed one clock) for all 440mx-initiated transactions. it is also an output during the data phase (delayed one clock) when the 440mx is the initiator of a pci write transaction, and when it is the target of a read transaction. pcirst# o pci reset . the 440mx asserts pcirst# to reset devices that reside on the pci bus. the 440mx asserts pcirst# during power-up and when a hard reset sequence is initiated through the rc (cf9h) register. pcirst# is driven inactive a minimum of 1 ms after pwrok is driven active. pcirst# is driven for a minimum of 1 ms when initiated through the rc register. pcirst# is asserted after pwrok is de-asserted in the str state. pgnt[3]# / gpio(30) pgnt[2:0]# i/o pci grants . 4 channels of bus master on the pci bus. pgnt[3]# is multiplexed with gpio. pirq(a-b)#, pirq(c-d)# / gpio(22:23) i/od pci interrupt requests . the pirqx# signals can be routed to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 or 15 as described in section 7.10.1.8. each pirqx# line has a separate route control register.
82443MX pciset 15 signal type description pirqc# and pirqd# are multiplexed with gpio. plock# i/o pci lock . indicates an exclusive bus operation and may require multiple transactions to complete. the 440mx asserts plock# when it is doing non- exclusive transactions on pci. plock# is ignored when pci masters are granted the bus. pme# / gpio(0) i / i/o pci power management event . driven by pci peripherals to wake the system from low-power states s1-s5. now included in the pci specification. preq[3]# / gpio(29) preq[2:0]# i/o pci requests . 4 channels of bus master on the pci bus. reqa# / gpio(2) i pc/pci dma request . see section 7.7 for a description. if the pc/pci request is not needed, this signal can be used as a gpio. serr# i/od system error . serr# can be pulsed active by any pci device that detects a system error condition. upon sampling serr# active, the 440mx can be programmed to generate an nmi, smi#, or interrupt. some internal conditions can also cause the 440mx to drive serr# active. stop# i/o stop . stop# indicates that the 440mx, as a target, is requesting an initiator to stop the current transaction. as an initiator, stop# causes the 440mx to stop the current transaction. stop# is an output when the 440mx is a target and an input when the 440mx is an initiator. stop# is three-stated from the leading edge of pcirst#. stop# remains three-stated until driven by the 440mx as a slave. trdy# i/o target ready . trdy# indicates the 440mx's ability to complete the current data phase of the transaction. trdy# is used in conjunction with irdy#. a data phase is completed when both trdy# and irdy# are sampled asserted. during a read, trdy# indicates that the 440mx, as a target, has placed valid data on ad[31:0]. during a write, it indicates the 440mx, as a target is prepared to latch data. trdy# is an input to the 440mx when the 440mx is the initiator and an output when the 440mx is a target. trdy# is three-stated from the leading edge of pcirst#. trdy# remains three-stated by the 440mx until driven as a target. table 7. ac97 signal description signal type description ac_bit_clk i ac97 bit clock . 12.288 mhz serial data clock ac_rst# o ac97 reset . master h/w reset ac_sdata_ in(0) i ac97 serial data in . serial tdm data input ac_sdata_ in(1) i ac97 serial data in . serial tdm data input
82443MX pciset 16 ac_sdata_ out o ac97 serial data out . serial tdm data output ac_sync o ac97 sync . 48 khz fixed rate sample sync table 8. interrupt signal description signal type description irq(14) i interrupt request 14 . this interrupt input is connected to the ide drive. serirq / gpio(7) i/od serial interrupt request . this pin conveys the serial interrupt protocol. this signal is muxed with gpio(7). table 9. rtc signal description signal type description rtcx1 specia l 32 khz crystal . connected to the 32.768 khz crystal. if no external crystal is used, then rtcx1 can be driven with the desired clock rate. rtcx2 specia l 32 khz crystal . connected to the 32.768 khz crystal. if no external crystal is used, then rtcx2 should remain floating. table 10. clocks, reset, plls and miscellaneous signal description signal type description clk48 i 48 mhz clock . this signal runs the usb controller. dclk i sdram clock . feedback reference from the external zero-delay sdram clock buffer. the 440mx uses this clock when accessing an sdram array. dclko o sdram clock out . 66 mhz sdram clock reference generated internally by the 440mx onboard pll. it feeds an external buffer that produces multiple copies for the dimms. hclkin i host clock in . this pin receives a buffered host clock. this clock is used by all of the 440mxs logic that resides is in the host clock domain. this clock is used by an internal pll to generate clock references for 66 mhz operations. during pos/str hclkin must be low. this is the same or identical clock that goes to processor . osc i oscillator clock . used for 8254 timers. runs at 14.31818 mhz. pciclk i pci clock . this is a buffered pci clock reference that is synchronously derived by an external clock synthesizer component from the host clock. this clock is used by all of the 440mxs logic that resides in the pci clock domain. during pos/str pclkin must be low.
82443MX pciset 17 table 11. usb signal description signal type description oc[1:0]# i overcurrent indicators . these signals set corresponding bits in the usb controller to indicate that an overcurrent condition has occurred. usbprt[0]+, usbprt[0]- i/o universal serial bus port 0 differential . bus data/address/command bus. usbprt[1]+, usbprt[1]- i/o universal serial bus port 1 differential . bus data/address/command bus. table 12. smbus signal description signal type description smbclk i/od smbus clock . smbus clock pin. external pullup required. smbdata i/od smbus data . smbus data pin. external pullup required. table 13. power management signal description signal type description batlow# / gpio(11) i / i/o battery low . this signal is on the resume plane. if the battery low function is not needed, then this signal is used as a general-purpose i/o pin. cpustp# o stop cpu clock . this signal is an output to the external clock generator to turn off the processor and memory clo cks. this is done prior to entering the c3 state, as well as the s1 and s2 states. exsmi# / gpio(24) i / i/o external system management interrupt . exsmi# is a falling edge-triggered input to the 440mx indicating that an external device is requesting the system to enter smm mode. when enabled, a falling edge on exsmi# results in the assertion of smi# to the processor. exsmi# is an asynchronous input to the 440mx. however, when the setup and hold times are met it is only required to be asserted for one pciclk. once de-asserted it must remain de-asserted for at least four pciclks to allow the edge detect logic to pcirst#. an external pullup should be placed on this signal if it is not used; otherwise it is not always guaranteed to be driven. exsmi# can cause an serr# (if enabled). this signal resides on the resume plane. if exsmi# is not used, this signal can be used as a gpio. lid / gpio(10) i / i/o lid . input from the lid button/switch. this signal can be used to generate wake events or interrupts. this signal is muxed with gpio(10). pcistp# o stop pci clock . this signal is an output to the external clock generator to turn off the pci clock.
82443MX pciset 18 signal type description pwrbtn# i power button . this signal causes the smi# or sci to request that the system enter a sleep state. if already in a sleep state, it causes a wake event. if pwrbtn# is pressed for four seconds, it causes an unconditional transition (power button override) to the s5 state with only the pwrbtn# available as a wake event. an override occurs even if the system is in the s1-s4 states. pwrok i power ok . when asserted, pwrok is an indication to the 440mx that str (suspend-to-ram) power plane and pciclk has been stable for at least 1 ms. pwrok can be driven asynchronously. when pwrok is negated, the 440mx asserts pcirst# and rstdrv. it also resets the processor. ri# / gpio(12) i / i/o ring indicate . when asserted, this signal indicates that a telephone ringing signal has been received by the modem and that the 440mx should wake up the system to accept data from the call. this signal is muxed with gpio(12). rsmrst# i resume well reset . used for resetting the resume well. if using a ps98 power supply, then no external rc circuit is required. otherwise, a 1 ms delay is needed. sus_stat# o suspend status . this signal is asserted by the 440mx to indicate that the system will be entering a low-power state soon. it can be used by peripherals as an indication that they should isolate their outputs that may be going to powered- off planes. susa# o power plane control. shuts off power to all non-critical systems when in the s1 (power-on suspend) or s2 (power-on suspend w/ full reset) state. this signal goes low to turn off the power. susb# o power plane control . shuts off power to all non-critical systems when in the s3 (suspend-to-ram) state. this signal goes low to turn off the power. susc# o power plane control . shuts power to all non-critical systems when in the s4 (suspend-to-disk) or s5 (soft off) states. this signal goes low to turn off the power. susclk o suspend clock . 32.768 khz. this output signal from the real time clock generator circuit is used as the refresh clock for the 440mx. this signal is always running, except in the suspend-to-disk or soft-off states. during reset: running after reset: running during pos, str: running thrm# / gpio(8) i / i/o thermal alarm . active low signal generated by external hardware to start the hardware clock throttling mode. this signal can also generate an smi# or an sci. this signal is muxed with gpio(8).
82443MX pciset 19 table 14. gpio signal description signal default type* description gpio[0,1,2,4,5, 6,7,8,9,10,11, 12,13,15,17,18, 20,21,22,23,24, 27,29,30] input general purpose i/o . handled by system processor. some of the 31 gpio signals are muxed with other functions. (see section 4.1.2 for the gpio definition.) 3.3v only or 3.3/5v (3.3v drive with 5v tolerant). see table 24 for details. gpio[3,14,16, 19,25,26,28] output general purpose i/o . handled by system processor. some of the 31 gpio signals are muxed with other functions. (see section 4.1.2 for the gpio definition.) 3.3v only or 3.3/5v (3.3v drive with 5v tolerant). see table 24 for details. note: *this table specifies the default direction of the pins selected as gpios (gpio_dir register dev #7, function 3, power management i/o space). table 15. x-bus signal description signal type description bioscs# o rom bios chip select . this chip select is driven active during read or write accesses to enabled bios memory ranges. dack(3)# / gpio(28) i/o dma acknowledge . the dack output lines indicate that a request for dma service has been granted by the 440mx. these lines should be used to decode the dma slave device with the ior# or iow# line to indicate selection. upon pcirst#, these lines are set inactive (high). dack3# is muxed with gpio(28). dack(2:0)# o dma acknowledge . the dack output lines indicate that a request for dma service has been granted by the 440mx. these lines should be used to decode the dma slave device with the ior# or iow# line to indicate selection. upon pcirst#, these lines are set inactive (high). dreq(3) / gpio(27) i/o dma request . the dreq lines are used to request dma service from the 440mx's dma controller. all inactive to active edges of dreq are assumed to be asynchronous. the request must remain active until the appropriate dackx# signal is asserted. dreq3 is muxed with gpio(27). dreq(2:0) i dma request . the dreq lines are used to request dma service from the 440mx's dma controller. all inactive to active edges of dreq are assumed to be asynchronous. the request must remain active until the appropriate dackx# signal is asserted. iochrdy i/o i/o channel ready . resources on the x-bus de-assert iochrdy to indicate that additional time (wait states) is required to complete the cycle. this signal is normally high on the x-bus.
82443MX pciset 20 signal type description ior# i/o i/o read . ior# is the command to an x-bus i/o slave device that the slave may drive data on to the x-bus data bus (sd[15:0]). the i/o slave device must hold the data valid until after ior# is negated. ior# is driven high upon pcirst#. during reset: high-z after reset: high during pos: high iow# i/o i/o write . iow# is the command to an x-bus i/o slave device that the slave may latch data from the x-bus data bus (sd[7:0]). iow# is driven high upon pcirst#. during reset: high-z after reset: high during pos: high irq12 (mouse irq) i interrupt request 12/ mouse interrupt . this pin provides a mouse interrupt function. config dev #7, offset 4e :bit 4 in the x-bus chip select register determines the functionality of irq12. when bit 4=0, the standard interrupt function is provided and this pin can be tied to the x-bus connector. when bit 4=1, the mouse interrupt function is provided and this pin can be tied to the irq12 output of the keyboard controller. when the mouse interrupt function is selected, a low-to-high transition on this signal is latched by the 440mx and an int is generated to the processor as irq12. an internal irq12 interrupt will continue to be generated until a reset or an i/o read access to address 60h (falling edge of ior#) is detected. after reset, this pin provides the standard irq12 function (as an input). irq8# / gpio(6) i / i/o irq8# is always an active low edge-triggered interrupt input (i.e., this interrupt cannot be modified by software). upon pcirst#, irq8# is placed in active-low edge-sensitive mode. this signal is muxed with gpio(6). during reset: high-z after reset: high-z during powerdown: high-z irq[3:7] i interrupt requests [3:7] . the irq signals provide both system board components and x-bus i/o devices with a mechanism for asynchronously interrupting the processor. the assertion mode of these inputs depends on the programming of the two elcr registers. when an elcr bit is programmed to a 0, a low-to-high transition on the corresponding irq line is recognized as an interrupt request. this "edge-triggered" mode is the 440mx default. when an elcr bit is programmed to a 1, a high level on the corresponding irq line is recognized as an interrupt request. this mode is "level-triggered" mode. irq1 (kbc irq) i keyboard interrupt . this is the interrupt from the keyboard controller. an internal flip-flop is placed between the pin and the 8259 to be compatible with keyboard controllers which only pulse irq1 to signal an interrupt. a low-to-high transition on irq1 can be latched by the 440mx. reads to port 60h clear the internal flip flop, at which time the flip-flop is armed for another low-to-high transition. kbccs# / o / i/o keyboard chip select . kbccs# is asserted during i/o read or write accesses
82443MX pciset 21 signal type description gpio(26) to kbc. this signal is muxed with gpio(26). mccs# / gpio(25) o / i/o microcontroller chip select . dedicated chip select for an external microcontroller. the i/o registers for the microcontroller are hard coded to i/o locations 62h and 66h. during reset: high after reset: high during pos: high this signal is muxed with gpio(25). memr# i/o memory read . memr# is the command to a memory slave that it may drive data onto the x-bus data bus. during reset: high-z after reset: high during pos: high memw# i/o memory write . memw# is the command to a memory slave that it may latch data from the x-bus data bus. during reset: high-z after reset: high during pos: high pcs(1)# / gpio(16) pcs(0)# / gpio(19) o / i/o programmable chip selects . this active low chip select is asserted for isa i/o cycles that hit the range programmed into the device monitors[9,10] function 3, pm i/o space. it is assumed that the peripheral selected via this pin resides on the x-bus. note: pcs(1:0)# pins are included in the gpio section (section 4.1.2). rstdrv o reset drive . the 440mx asserts rstdrv to reset devices that reside on the x- bus. the 440mx asserts this signal during a hard reset and during power-up. rstdrv is asserted during power-up and de-asserted after pwrok is driven active. rstdrv is also driven active for a minimum of 1 ms if a hard reset has been programmed in the rc register. during reset: high after reset: low during pos: low sa[18:0] i/o system address bus . these address lines define the selection with the granularity of one byte within the 512kb section of memory. for i/o accesses, only sa(15:0) are used. the 440mx always owns the x-bus during slave and legacy dma cycles. sa[18:0] are at an unknown state upon pcirst#. during a dma i/o cycle, the addr ess bus will be driven to 00h to prevent other i/o devices from falsely decoding the cycle. during reset: high-z after reset: undefined during pos: last address
82443MX pciset 22 signal type description sd[7:0] i/o system data bus . sd[7:0] provide the 8-bit data path for devices residing on the x-bus. the 440mx three-states sd[7:0] during pcirst#. sysclk o x-bus system clock . sysclk is the reference clock for the x-bus. it drives the x-bus directly. the sysclk is generated by dividing pciclk by four. during reset: running after reset: running during pos: low note: this clock is needed for external ir. tc o terminal count . the 440mx asserts tc to dma slaves as a terminal count indicator. the 440mx asserts tc after a new address has been output, if the byte count expires with that transfer. when all the dma channels are not in use, tc is negated (low). upon pcirst#, tc is inactive. during reset: high after reset: low during pos: high zerows# i zero wait states . an isa slave asserts zerows# after its address and command signals have been decoded to indicate that the current cycle can be shortened. a 16-bit isa memory cycle can be reduced to two sysclks. an 8-bit memory or i/o cycle can be reduced to three sysclks. zerows# has no effect during 16-bit i/o cycles. if iochrdy is negated and zerows# is asserted during the same clock, then zerows# is ignored and wait states are added as a function of iochrdy. notes: 1. x-bus signals are 5v tolerant. 2. since the 440mx does not support the secondary ide channel, irq15 is no longer available. however, serirq and pci interrupts can be steered to generate interrupt 15 to the interrupt controller. 4.1.2 power and ground pins table 16. core power pins name description v cc 3.3v for core. this power is shut off during some low-power states. v ss v ss core. table 17. host i/f power pins name description gtlref gtl+ buffer voltage reference input for the mobile celeron processor or pentium ii processor i/f.
82443MX pciset 23 vtt[b:a] gtl+ termination voltage used for early clamps. table 18. rtc power pins name description v cc rtc power for rtc well. 2.0v-3.3v. this power is not expected to be shut off unless the rtc battery is removed or drained, or unless an external rtc is used. table 19. usb power pins name description v cc usb power for usb logic. 3.3v. this power will not be shut off in low-power states except for mechanical off. v ss usb ground for usb. note: v cc sus and v cc usb should both be on simultaneously. table 20. resume power pins name description v cc sus 3.3v for resume well. this power is not expected to be shut off unless the system is unplugged or the main battery is completely drained for a mobile system. note: v cc sus and v cc usb should both be on simultaneously. table 21. vref power pins name description refv cc reference for 5v tolerance on inputs. this power is shut off in some low-power states. 4.2 gpio definition the 440mx includes 31 gpios, twelve of which are located in the resume well. the gpios located in the resume well have their reset control changed from pcirst# to rsmrst#, and as a result retain their programming from s3-s5. they retain their values throughout and after suspend and are not reset to their default values. the well column in table 22 lists all gpios in the resume well that are affected by this change. table 22. gpio pins programmed through config. dev.7, fn. 0 gpio pins well input output/od device activity monitor default function, value gpio(0)* resume pme# pme#, 1 gpio(1)* resume gpi(1) gpio(1)
82443MX pciset 24 gpio pins well input output/od device activity monitor default function, value gpio(2) reqa# gpio(2) gpio(3) gnta# gpio(3) gpio(4)* resume generic 0 generic 0 gpio(5) pide1 pide1 gpio(6) resume irq8# (see gpio pin default priority #6) gpio(6) gpio(7) serirq serirq gpio(7) gpio(8) core thrm# thrm#, 1 gpio(9)* resume gpio(10)* resume lid lid, 0 gpio(11)* resume batlow# batlow#, 1 gpio(12)* resume ri# ri#, 1 gpio(13) audio audio gpio(14) spkr fdd spkr, 0 gpio(15) serial a seriala gpio(16) pcs1# serial b pcs1#, 1 gpio(17)* resume lpt lpt gpio(18)* resume generic 1 generic 1 gpio(19) pcs0# gfx pcs0#, 1 gpio(20)* resume cardbus 0 cardbus 0 gpio(21) zerows# cardbus 1 zerows#, 1 gpio(22) pirqc# pirqc# pirqc#, 1 gpio(23) pirqd# pirqd# pirqd#, 1 gpio(24)* resume exsmi# exsmi# exsmi#, 1 gpio(25) mccs# mccs#, 1 gpio(26) kbccs# kbccs#, 1 gpio(27) dreq3 dreq3,0 gpio(28) dack3# dack3#, 1 gpio(29) preq3#
82443MX pciset 25 gpio pins well input output/od device activity monitor default function, value gpio(30) pgnt3# notes: 1. gpio(x)* is capable of waking from sleep states. 2. gpio[0, 4, 9, 17, 18, 20] are capable of generating sci and smi like gpio(1). these new gpios can generate resume events. 3. the following gpio registers: gpo_reg, gpio_dir and gpio_cntrl (device #7, function 3, pm i/o space) are in the resume well and are reset by rsmrst# (unlike those which are not in the resume well and which are reset by pcirst#), and as a result retain their programming from s3-s5. they retain their values throughout and after suspend and are not reset to their default values. the gpio pin default priority is as follows : 1. all gpio pins controlled by gpio_cntrl (muxed gpio control register, device #7, function 3, power management system i/o space) always default to functional pins. these pins can be used as gpios if the corresponding bit in the muxed gpio control register is 0. to use as a gpi or gpo the corresponding gpio_dir bit must be set to the appropriate value. 2. the following four gpio pins controlled by the gscr register (general signal and functional configuration register - device #7, function 0) default to gpi/gpo:  reqa#  gnta#  serirq  irq8# 3. priority between gpio control registers (i.e., muxed gpio control and gscr registers) and the gpio direction register (gpio_dir register) is defined as follows: when a functional signal is selected via these gpio control registers the values programmed in the gpio_dir register are ignored. 4. for the gpio(14) pin with three functions (spkr, fdd device monitor, gpio), the priority is as follows: it will be used as spkr if gpio_cntrl register (muxed gpio control register, device #7, function 3, pm i/o space) bit 1 is programmed as 1. if the muxed gpio control register is programmed as 0, then it is used as a an fdd device monitor when the gpi_en_dev5 (muxed gpio control register, device #7, function 3) bit is set. if both the muxed gpio control register bit 1 and gpi_en_dev5 are set to 0, then the pin is used as a gpio (gpio_dir register programs it for either input or output). 5. the signals listed in table 23 do not resume the system when used as gpios. they resume the system when programmed as functional pins (i.e., pme#, lid, batlow#, exsmi# or ri#). 6. gpio(6)/irq8# is in the resume well but will not wake the system from the s3/s4/s5 states. table 23. system resume with gpio signals programmed as functional pins gpio functional pin gpio(0) pme# gpio(10) lid gpio(11) batlow#
82443MX pciset 26 gpio(12) ri# gpio(24) exsmi# 4.3 power rail overview figure 2 illustrates the power rails of the entire 440mx platform. 440mx s y stem memor y ( sdram ) dimm#1 graphic controller crt lcd panel clock gen. ckm66 ide drive ( 2 ) ac'97 codec mobile celeron tm processor / pentium tm ii processor power mana g ement gpio smbus pci ( 3.3v/5v ) cardbus controller s y stem memor y ( sdram ) dimm#0 66 mhz, ( 3.3v ) 3.3v usb ( 2 ports ) 66 mhz, gtl processor i/f ( incl. reset ) hclkin (2.5v) pclkin ( 3.3v ) ioclk 3.3v 3.3v 3.3v/5v 3.3v 3.3v/5v 3.3v/5v cpu side band si g nals ( 2.5v ) x-bus ( 8-bit ) 3.3/5v figure 2. platform power rails
82443MX pciset 27 4.4 power-up state initial value the signal states immediately after reset (pcirst#) and during pos/str (power-on suspend and suspend-to-ram states) are defined using the following headings: re state during reset sr state immediately following reset (pcirst#) sp state during pos/str iso signal is isolated during pos/str the signal states are defined using the following nomenclature: z three-stated l driven low h driven high dr driven to active logic state u undefined 4.5 power-on reset pin values table 24 lists the input/output pin values before and after reset, pos, str, std and mechanical off. the pu/pd column indicates whether an internal or an external pull-up or pull-down resistor is required. internal pull-up/pull-down resistors are used to set default strapping values. the internal resistors are disabled after pcirst# goes inactive. table 24. power-on reset values by signal group signal group signal power plane buffer type external pu/pd during reset after reset during pos during str during std mech. off host a20gate main 3.3/5v no input input input hi-z pwrdn pwrdn interface signals (1) a20m# main od pu note(7) hi-z last or a20gate hi-z pwrdn pwrdn ads# (4) main gtl+ hi-z hi-z hi-z hi-z pwrdn pwrdn bnr# (4) main gtl+ hi-z hi-z hi-z hi-z pwrdn pwrdn bpri# (4) main gtl+ hi-z hi-z hi-z hi-z pwrdn pwrdn breq0# (6) main gtl+ hi-z/low hi-z/low hi-z hi-z pwrdn pwrdn cpurst# (2) main gtl+ pd low hi-z hi-z hi-z pwrdn pwrdn dbsy# (4) main gtl+ hi-z hi-z hi-z hi-z pwrdn pwrdn
82443MX pciset 28 signal group signal power plane buffer type external pu/pd during reset after reset during pos during str during std mech. off defer# (4) main gtl+ hi-z hi-z hi-z hi-z pwrdn pwrdn drdy# (4) main gtl+ hi-z hi-z hi-z hi-z pwrdn pwrdn ferr# main 2.5/3v no input input input input pwrdn pwrdn ha[31:3]# (3) main gtl+ hi-z hi-z hi-z hi-z pwrdn pwrdn hd[63:0]# (4) main gtl+ hi-z hi-z hi-z hi-z pwrdn pwrdn hitm# (4) main gtl+ hi-z hi-z hi-z hi-z pwrdn pwrdn hlock# (4),(5) main gtl+ hi-z hi-z hi-z hi-z pwrdn pwrdn hreq[4:0]# (4) main gtl+ hi-z hi-z hi-z hi-z pwrdn pwrdn htrdy# (4) main gtl+ hi-z hi-z hi-z hi-z pwrdn pwrdn ignne# main od pu note(7) hi-z hi-z hi-z pwrdn pwrdn init# main od pu hi-z hi-z hi-z hi-z pwrdn pwrdn intr main od pu note(7) low low low pwrdn pwrdn nmi main od pu note(7) low low low pwrdn pwrdn rcin# main 3.3/5v no input input input hi-z pwrdn pwrdn rs[2:0]# (4) main gtl+ hi-z hi-z hi-z hi-z pwrdn pwrdn smi# main od pu hi-z hi-z hi-z hi-z pwrdn pwrdn stpclk# main od pu hi-z hi-z low hi-z pwrdn pwrdn ide interface pda[2:0] main 3.3/5v no low un- defined low hi-z pwrdn pwrdn signals pdcs1# main 3.3/5v no high high high hi-z pwrdn pwrdn pdcs3# main 3.3/5v no high high high hi-z pwrdn pwrdn pdd[15: 0] main 3.3/5v no hi-z input hi-z hi-z pwrdn pwrdn pddak# main 3.3/5v no high high high hi-z pwrdn pwrdn pddrq main 3.3/5v pd input input input hi-z pwrdn pwrdn pdior#/ pdwstb/ prdmardy# main 3.3/5v no high high high hi-z pwrdn pwrdn pdiow#/ pdstop main 3.3/5v no high high high hi-z pwrdn pwrdn piordy/ pdrstb/ pwdmardy# main 3.3/5v pu input input input hi-z pwrdn pwrdn test spkr / main 3.3v no low low last hi-z pwrdn pwrdn
82443MX pciset 29 signal group signal power plane buffer type external pu/pd during reset after reset during pos during str during std mech. off signals gpio[14] test# resume 3.3v pu input input input input input pwrdn pci bus ad[31:0] main 3.3/5v no low driven low low pwrdn pwrdn interface c/be[3:0]# main 3.3/5v no low driven low low pwrdn pwrdn signals clkrun# main 3.3v pu low low low low pwrdn pwrdn devsel# main 3.3/5v pu hi-z hi-z hi-z hi-z pwrdn pwrdn frame# main 3.3/5v pu hi-z hi-z hi-z hi-z pwrdn pwrdn gnta# / gpio(3) main 3.3/5v no high/ gpio state high/ gpio state high/ gpio state hi-z pwrdn pwrdn irdy# main 3.3/5v pu hi-z hi-z hi-z hi-z pwrdn pwrdn par main 3.3/5v no low driven low low pwrdn pwrdn pcirst# main 3.3/5v no low high high low pwrdn pwrdn pgnt[3]# / gpio(30) pgnt[2:0]# main 3.3/5v pu hi-z high hi-z hi-z pwrdn pwrdn pirq[a-b]# main 3.3/5v pu hi-z hi-z hi-z hi-z pwrdn pwrdn pirq[c-d]# / gpio(22,23) main 3.3/5v pu hi-z hi-z hi-z hi-z pwrdn pwrdn plock# 3.3/5v pu hi-z hi-z hi-z hi-z pwrdn pwrdn pme# / gpio(0) resume 3.3v hi-z hi-z driven driven driven pwrdn preq[3]# / gpio(29) preq[2:0]# main 3.3/5v pu hi-z hi-z hi-z hi-z pwrdn pwrdn reqa# / gpio(2) main 3.3/5v no input input input hi-z pwrdn pwrdn serr# main 3.3/5v pu hi-z hi-z hi-z hi-z pwrdn pwrdn stop# main 3.3/5v pu hi-z hi-z hi-z hi-z pwrdn pwrdn trdy# main 3.3/5v pu hi-z hi-z hi-z hi-z pwrdn pwrdn ac97 (9) ac_bit_clk main 3.3v none running running low hi-z pwrdn pwrdn signals ac_rst# resume 3.3v no low low high low low pwrdn ac_sdata_ in[1:0] resume 3.3v none input input driven low low pwrdn
82443MX pciset 30 signal group signal power plane buffer type external pu/pd during reset after reset during pos during str during std mech. off ac_sdata_ out main 3.3v none low low low hi-z pwrdn pwrdn ac_sync main 3.3v none low low low low pwrdn pwrdn interrupt signal serirq/ gpio[7] main 3.3/5v pu gpio state gpio state hi-z/ gpio state hi-z pwrdn pwrdn rtc signals rtcx[2:1] rtc 3.3v no special special special special special special clocks/ reset/ clk48 main 3.3/5v no input input input iso pwrdn pwrdn pll/ misc. osc main 3.3/5v no input input input iso pwrdn pwrdn signals pciclk main 3.3/5v no running running low low pwrdn pwrdn usb signals usbprt0[+:-] usb/ resume 3.3v pd hi-z hi-z hi-z hi-z hi-z pwrdn usbprt1[+:-] usb/ resume 3.3v pd hi-z hi-z hi-z hi-z hi-z pwrdn oc[1:0]# resume 3.3v pu input input input input input pwrdn smbus smbclk resume 3.3v pu hi-z hi-z hi-z hi-z hi-z pwrdn signals smbdata resume 3.3v pu hi-z hi-z hi-z hi-z hi-z pwrdn power mgmt signals batlow# / gpio[11] resume 3.3v no (10) input input input/ gpio state input/ gpio state input / gpio state pwrdn cpustp# main 3.3/5v no high high low iso pwrdn pwrdn exsmi#/ gpio[24] resume 3.3v no (10) input input input/ gpio state input/ gpio state input/ gpio state pwrdn lid / gpio[10] resume 3.3v no (10) input input input/ gpio state input/ gpio state input/ gpio state pwrdn pcistp# main 3.3/5v no high high low iso pwrdn pwrdn pwrbtn# resume 3.3v no input input input input input pwrdn pwrok rtc 3.3v no input input input input input input ri# / gpio[12] resume 3.3v no (10) input input input/ gpio state input/ gpio state input/ gpio state pwrdn rsmrst# rtc 3.3v no input input input input input input sus_stat# resume 3.3v no low high low low low pwrdn susa# resume 3.3v no high high low low low pwrdn
82443MX pciset 31 signal group signal power plane buffer type external pu/pd during reset after reset during pos during str during std mech. off susb# resume 3.3v no high high high low low pwrdn susc# resume 3.3v no high high high high low pwrdn susclk resume 3.3v no running running running running low pwrdn thrm# / gpio[8] main 3.3v no (10) input input input/ gpio state hi-z pwrdn pwrdn isa / bioscs# main 3.3/5v no high high high hi-z pwrdn pwrdn eio / x-bus signals dack[3]# / gpio(28) dack[2:0]# main 3.3/5v no high high high hi-z pwrdn pwrdn dreq[3] / gpio(27) dreq[2:0] main 3.3/5v pd input input input hi-z pwrdn pwrdn iochrdy main 3.3/5v pu hi-z hi-z hi-z hi-z pwrdn pwrdn ior# main 3.3/5v pu hi-z hi-z high hi-z pwrdn pwrdn iow# main 3.3/5v pu hi-z hi-z high hi-z pwrdn pwrdn irq[1] / irq[3:7] / irq[12] main 3.3/5v pu input input input hi-z pwrdn pwrdn irq8#/ gpio[6] resume 3.3v pu input input/ gpio state input/ gpio state input/ gpio state input/ gpio state pwrdn kbccs# / gpio(26) main 3.3/5v no high high high hi-z pwrdn pwrdn mccs# / gpio(25) main 3.3v no high high high hi-z pwrdn pwrdn memr# main 3.3/5v pu hi-z hi-z high hi-z pwrdn pwrdn memw# main 3.3/5v pu hi-z hi-z high hi-z pwrdn pwrdn pcs[1:0]# / gpio(16,19) main 3.3/5v no high high last hi-z pwrdn pwrdn rstdrv main 3.3/5v pu high low low hi-z pwrdn pwrdn sa[18:0] main 3.3/5v no un- defined un- defined last hi-z pwrdn pwrdn sd[7:0] main 3.3/5v pu hi-z un- defined last hi-z pwrdn pwrdn sysclk main 3.3/5v no running running low hi-z pwrdn pwrdn tc main 3.3/5v no high low low hi-z pwrdn pwrdn
82443MX pciset 32 signal group signal power plane buffer type external pu/pd during reset after reset during pos during str during std mech. off zerows# / gpio(21) main 3.3/5v pu input input input hi-z pwrdn pwrdn general purpose gpio[1,4,9,17, 18,20] resume 3.3v no (10) input/ output input/ output gpio state gpio state gpio state pwrdn input / output signals gpio[2,3,5,7, 13,14,15,16, 19,21,22,23, 25,26,27,28, 29,30] main 3.3/5v no (10) input/ output input/ output gpio state hi-z pwrdn pwrdn notes: 1. all host interface signals have their clamps disabled in suspend, include gtl+ termination, and are isolated during pos/str. 2. cpurst# is always active when pcirst# is asserted. for cold reset and resume from str, cpurst# is de-asserted 1 ms after pcirst# de-assertion. for resume from pos (of which cpurst# option is enabled), cpurst# is de-asserted 1 ms after sus_stat# de-assertion. 3. when pcirst# is asserted, the enable signal to the buffer is de-asserted. therefore, the output is floated in the next clock. ha[7]# and ha[15]# buffers are enabled when cpurst# is active and the strap values from the ma lines are driven out. these two signals are driven until 4 clocks after cpurst# de-assertion. 4. the enables to these buffers are de-asserted combinatorially from pcirst#. therefore, the buffer is floated in the next clock. 5. this signal is not driven since it is an input only (functionally). 6. breq0# is driven l two clocks before cpurst# de-assertion and remains l for two clocks after cpurst# de- assertion. it is otherwise never driven by the 440mx. during suspend, breq0#, as the rest of host bus signals, is not driven and the input buffer is isolated. 7. during reset, a20m#, ignne#, nmi and intr values are set by the 440mx (for bus fraction ratio). 8. upon rsmrst#, resume well gpios revert back to their functional state. upon pcirst#, resume well gpios maintain their previous pin state. 9. all ac link signals have internal pullups/pulldowns. 10. any unused input should be pulled inactive.
82443MX pciset 33 table 25. dram interface signals name reset/ cold reset after reset entering pos/str state during pos/str (also optional reset) std/ mech. off internal pu/pd clamp disabled in suspend comments notes cke[3:0] h h cke l pwrdn no clamps cke used for self ref cmd when enter sp. cke remains l during sp. cs[3:0]# un- defined h self ref h pwrdn no clamps cke used for self ref cmd when enter sp. dqm[7:0] h h h h pwrdn no clamps ma[10] z dr dr dr pwrdn 50k pu no clamps used for straps, z during reset and suspend. ma[11]# z dr dr dr pwrdn 50k pu no clamps used for straps, z during reset and suspend. ma[13], ma[12]#, ma[9:0]# zdrdrdr pwrdn 50k pd no clamps used for straps, z during reset and suspend. md[63:0] un- defined dr dr dr pwrdn yes scas# h h l l pwrdn no clamps scas# is used for self ref cmd when enter sp.
82443MX pciset 34 name reset/ cold reset after reset entering pos/str state during pos/str (also optional reset) std/ mech. off internal pu/pd clamp disabled in suspend comments notes sras# h h l l pwrdn no clamps sras# is used for self ref cmd when enter sp. we# h h h h pwrdn no clamps table 26. miscellaneous signals name during cold reset before reset after reset state during pos/str isolate to h in suspend pu/pd notes dclk (input) pulldown enabled during suspend:  driven by ext clk buffer in normal config, this buffer is not powered down in sp, thus resistor is disabled.  to avoid floating, a pulldown is used. also connected during cold reset. dclko (output) dr dr dr l or h ext clk buffer remains powered during str and normal config. there is no clk buffer in mmo config. hclkin (input) pulldown enabled int pd 100k weak pulldown keeps clk low in str (when synth. may be powered down) while leaks very little current in pos. resistor is disabled in normal operation. also connected during cold reset.
82443MX pciset 35 name during cold reset before reset after reset state during pos/str isolate to h in suspend pu/pd notes pciclk (input) pulldown enabled int pd 100k weak pulldown keeps clk low in str (when synth. may be powered down) while leaks very little current in pos. resistor is disabled in normal operation. also connected during cold reset. pcirst# pulldown enabled pulldown enabled int pd 100k internal pulldown is connected during suspend and cold reset. notes : 1. all miscellaneous signals are cmos buffers. 5v tolerance: although the 440mx never drives an output above 3.3v, many of the i/o buffers and input buffers can tolerate external signals driven up to 5v. the following signals must be 5v tolerant:  all pci inputs and i/os  al ide inputs and i/os  serirq  irq14 signals located in the resume well are 3.3v tolerant only. 4.6 power-up/reset strap options table 27 lists all power-up options that are loaded into the 440mx during system reset. the 440mx is required to float all signals connected to straps during system reset (pcirst# active) and keep them floated for a minimum of four host clocks after the end of a reset sequence. the first column lists the signal that is sampled to obtain the strapping option. the second column shows the register into which the strapping option is loaded. the third column describes the functionality that the strapping selects. note that all signals used to select power-up strap options are connected to either internal pull-down or pull-up resistors of approximately 50 kohms. that selects a default mode on the signal during reset. to enable different modes, external pullups or pulldowns of approximately 10k ohms can be connected to particular signals. these pull-up or pull- down resistors should be connected to the 3.3v power supply. the gtl+ signals are connected to the v tt through the normal pullups. processor bus straps controlled by the 440mx (e.g., a7# and a15#), are driven active at least six clocks prior to the active-to-inactive edge of cpurst# and driven inactive four clo cks after the active-to-inactive edge of the cpurst#.
82443MX pciset 36 table 27. power-up options during reset signal register name/bit description ha[15]# none quick start select. the value on ha[15]# sampled at the rising edge of cpurst# reflects whether the quick start stop clock mode is enabled in the processor. ha[7]# none in-order queue depth status. the value on ha[7]# sampled at the rising edge of cpurst# reflects whether the ioqd is set to 1 or the maximum allowable by the processor bus. if the maximum processor bus in-order queue depth is selected, the 440mx will throttle it to 4 by asserting bnr# appropriately as per the processor bus protocol. ma12# nbxcfg[13] reserved. strap to a 1 internally. ma11# nbxcfg[2] in-order queue depth enable. if ma11# is strapped to 0 during the rising edge of pcirst#, then the 440mx will drive ha[7]# low during the cpurst# de-assertion. this forces the processor bus to be configured for non-pipelined operation. if ma11# is strapped to 1 (default), then the 440mx does not drive ha[7]# low during reset, and if ha[7]# is sampled in default non-driven state (i.e., pulled up as far as gtl+ termination is concerned) then the maximum allowable queue depth by the processor bus protocol is selected (i.e., 8). note that in this case external logic supplied by the oem can be used to drive ha[7]# and select the proper mode. if the maximum theoretical queue depth (i.e., 8) is selected by keeping ha[7]# de-asserted during reset, the 440mx uses the bnr# mechanism to throttle the processor bus to a maximum of four pipelined transactions. ma[11]# ioqd 01 1max. ma10 pmcr[3] quick start select. the value on this pin at reset determines which stop clock mode is used. if ma10 = 1 during the rising edge of pcirst#, then the 440mx drives ha[15]# low during cpurst# de-assertion. this configures the processor for quick start mode. note: the default mode should be the active state of the signal used for strapping. this sets the processor for quick start mode and the 440mx drives ha[15]# low during cpurst# de-assertion. this signal is internally tied to a 50 kohm pullup. ma8# none host_hfv (high frequency vco). an internal pulldown (a minimum of 50 kohms) is used to select host_hfv to a 0 as a default, indicating the host pll is set to the slower vco speed. an external pullup may be used if a later decision is made to select the fast host pll speed.
82443MX pciset 37 4.7 cpu reset the 440mx integrates the external logic previously required by the 443bx for determining the processor bus fraction and frequency multiplier. during a power-on reset, the pull-up/pull-down status on the four pins ma[13], [9, 7, 1]# are used to internally drive a20m#, ignne#, nmi and intr for speed strapping to the processor. after power-on reset, the a20m#, ignne#, nmi and intr are restored to normal functionality. the pin assignment to the ma is shown as follows:  ma[13] - nmi  ma[9]# - intr  ma[7]# - ignne#  ma[1]# - a20m# table 28 shows the mobile celeron processor / pentium ii processor frequency ratios for these pin assignments. table 28. mobile celeron? processor / pentium ? ii processor frequency ratios core/bus ratio nmi intr ignne# a20m# 2/11 (366 mhz) l h h h 1/5 (333 mhz) l l h h 2/9 (300 mhz) l h l h 1/4 (266 mhz) l l l h 2/7 (233 mhz) l h h l safe ratio (default) l l l l note: ma[13], [9, 7, 1]# signals have internal pulldowns to select the default, safe front-side-bus ratio which is processor dependa nt. the 440mx enables these internal pulldowns on the ma[13], [9, 7, 1]# pins only during reset. note: the 440mx does not drive strapping signals during a reset sequence. proper strapping must be used to define logical values for these signals. an external resistor can override the default value provided by the internal pull-up or pull-down resistor.
82443MX pciset 38 5. power planes 5.1 overview table 29 provides an overview of the four main power planes for the 440mx. table 29. power planes plane voltage i/o, core this plane is powered by the main battery. assumed to be 3.3v. when the system is in the s4, s5 or g3 state, this plane is assumed to be shut. in s3, this plane is still powered. resume this plane is powered by either the main battery or the ac power. rtc this plane is powered by the rtc battery. when other power is available (from the main battery), external diode coupling provides power to reduce rtc battery drainage. this plane is assumed to operate from 3.3v down to 2.0v. 5.2 rtc power plane table 30 lists the rtc power plane signals. these signals must be powered to maintain the system in the soft off state. table 30. rtc well signals signal usage pwrok input indicates that the str power plane is ok. used to isolate the rtc and resume wells from the main well. rsmrst# input indicates that the resume well should reset and that the rtc well should isolate from the resume well. rtcx1, x2 connections to the 32.768 khz crystal. 5.3 resume power plane table 31 lists the signals that reside in the resume well. these signals must be powered to maintain the system in all states, except the mechanical off state.
82443MX pciset 39 table 31. resume well signals signal usage ac_rst# ac_sdata_in (1:0) batlow# if batlow# is enabled on gpio(12) exsmi# if exsmi# is enabled (via muxed gpio register of configuration device 7, function 0) gpio[0,1,4,6,9,10, 11,12,17,18,20, 24] irq8# gpio(6) lid if lid is enabled on gpio(10) oc[1:0]# pme# if pme# is enabled on gpio(0) pwrbtn# ri# if ri# is enabled on gpio(12) smbclk smbdata sus_stat# susa# susb# susc# susclk test# usbprt[1:0]+, usbprt[1:0]-
82443MX pciset 40 6. system address map 6.1 addressable memory support a mobile celeron processor system based on the 440mx supports 4 gb of addressable memory space and 64k+3 bytes of addressable i/o space. (the mobile celeron processor bus i/o addressability is 64k+3 bytes.) the programmable memory address space under the 1 mb region which is divided into regions can be individually controlled with programmable attributes such as disable, read/write, write only, or read only. attribute programming is described in the programmable attribute map registers in pci configuration space. this section focuses on how the memory space is partitioned and how these separate memory regions are used. the i/o address space is explained at the end of this section. although the pentium ii processor family supports addressing of memory ranges larger than 4 gb, it is assumed that software running on a the 440mx system will never address physical memory above 4 gb (see figure 3). 6.2 memory map note: the internal pci bus between the north bridge/cluster and the south bridge/cluster is pci bus number 0. all cycles from the north bridge/cluster or external pci bus that appear on the internal pci bus are either positively or subtractively decoded by the south bridge/cluster, depending on the mode selected. all cycles from the south bridge/cluster or external pci bus that appear on the internal pci bus are positively decoded by the north bridge/cluster and claimed only if there is an address match. cycles between the north and south bridge/cluster are also broadcast to the external pci bus. thus the external pci bus which interfaces to other pci devices is logically the same bus as the internal pci bus, i.e., pci bus #0. table 32 summarizes the memory address space supported. the we and re attributes refer to write enable and read enable.
82443MX pciset 41 upper bios area (64kb) lower bios arrea (64kb) 2xpansion card bios & buffer area (128kb) optional fixed memory hole (128kb) dos area (512kb) standard video memory (smm memory) 128kb 0fffffh 0f0000h 0effffh 0e0000h 0dffffh 0c0000h 0bffffh 09ffffh 080000h 07ffffh 000000h 0a0000h 1mb 960kb 896kb 768kb 640kb 512kb pci memory range optional ext. pci mem. hole dos compatibility memory 4g 256m (max. tom) 16m 15m 1m 640k 512k 0 82440mx chipset memory address 82440mx memor y ma p main dram range optionally for agp in bx figure 3. memory address map table 32. memory segment attributes memory range (addresses in hex) attributes target dependency/comments 00000000 - 0007ffff none always mapped to main memory 0 to 512k dos region 00080000 - 0009ffff none configurable as external pci memory or main memory 512k to 640k dos region 000a0000 - 000bffff none mapped to external pci memory in normal mode; mapped to main memory in smm mode video buffer in normal mode; smm space in smm mode. 000c0000 - 000dffff we/re external pci memory for pci add-in card add-on bios.
82443MX pciset 42 memory range (addresses in hex) attributes target dependency/comments 000e0000 - 000effff we/re rom bios we/re attributes in pam registers control whether this range is directed to main memory (only), or gets forwarded to rom bios. 000f0000 - 000fffff we/re rom bios we/re attributes in pam registers control whether this range is directed to main memory (only), or gets forwarded to rom bios. 00100000 - tom (top of memory) none main memory tom is set by tom registers, and is a maximum of 256 mb. (tom + 1) - febfffff none external pci memory fec00000 - fecfffff none reserved in other systems, this range may be used for i/o apics. fed00000 - ffbfffff we/re external pci memory ffc00000 - fffeffff we/re rom bios or pci memory destination based on enable bits in rom bios decode enable register at offset e3h, device 7, function 0. ffff0000 - ffffffff we/re rom bios enable for this range in rom bios decode enable register at offset e3h, device 7, function 0 is hardwired to 1. this range is always targeted to rom bios. 6.2.1 compatibility area table 33 shows how the compatibility memory area from 0-1 mb (0000 0000h - 0010 0000h) is divided into address regions. table 33. compatibility memory area address range memory area 0 - 512 kb dos area 512 - 640 kb dos area / optional fixed memory hole 640 - 768 kb video buffer area 768 - 896 kb in 16kb sections (total of 8 sections) expansion area 896 - 960 kb in 16kb sections (total of 4 sections) extended system bios area
82443MX pciset 43 960 kb - 1 mb memory (bios area) system bios area there are sixteen memory segments in the compatibility area. thirteen of the memory ranges can be enabled or disabled independently for both read and write cycles. one segment (512k-640k) can be mapped to either main dram or pci. this section describes the various memory regions. 6.2.1.1 dos area (00000h-9fffh; 0 - 640 kb) the dos area is 640 kb in size and it is further divided into two parts. the 512-kb area at 0 to 7ffffh is always mapped to the main memory, while the 128-kb address range from 080000 to 09ffffh can be mapped to external pci or to main dram. by default this range is mapped to main memory and can be declared as a main memory hole (accesses forwarded to external pci) via the fdhc configuration register. 6.2.1.2 video buffer area (a0000h-bffffh; 640 - 768 kb) the 128-kbyte graphics adapter memory region is mapped to a legacy video device on external pci (typically a vga controller). the attribute bits do not control this area. processor-initiated cycles in this region are always forwarded to external pci for termination. this region is also the default region for smm space. the smram control register controls how smm accesses to this space are handled. 6.2.1.3 expansion area (c0000h-dffffh; 768 - 896 kb) this 128-kbyte expansion region is divided into eight 16-kbyte segments. each segment can be assigned one of four read/write states in main memory: read-only, write-only, read/write, or disabled. typically, these blocks reside on the external pci memory and are therefore given attribute "disabled" in main memory. memory that is disabled is not remapped. 6.2.1.4 extended system bios area (e0000h-effffh; 896 - 960 kb) this 64-kbyte area is divided into four 16-kbyte segments. each segment can be assigned independent read and write attributes so that reads and writes can be independently mapped to main dram or to the rom bios. typically, this area is used for ram or rom. memory segments that are disabled are not remapped elsewhere. 6.2.1.5 system bios area (f0000h-fffffh; 960 kb - 1 mb) this area is a single 64-kbyte segment. this segment can be assigned read and write attributes. it is by default (after reset) read/write disabled in main memory so that cycles are forwarded to the x-bus (rom bios). by manipulating the read/write attributes, the x-bus-based bios can shadowed into main dram. when disabled, this segment is not remapped. 6.2.2 extended memory area this memory area covers the 0010 0000h (1 mb) to ffff ffffh (4 gb-1) address range and is divided into the following regions:  main dram memory from 1 mb to the top of main memory; maximum tom is 128/256 mb, using 16mb/64mb/128mb dram technology.
82443MX pciset 44  pci memory space from the top of main memory to 4 gb, which includes the following two specific ranges:  high bios area from 4 gb  2 mb to 4 gb 6.2.2.1 main dram address range (0010_0000h to top of main memory) the address range from 1 mb to the top of main memory is mapped to the main dram address range. all accesses to addresses within this range will be forwarded to the main dram memory unless a hole in this range is created using the fixed hole as controlled by the fdhc register. accesses within this hole are forwarded to the external pci bus. the range of physical dram memory disabled by opening the hole is not remapped to the top of memory. 6.2.2.2 extended smram address range (top of main memory - tseg_sz to top of main memory) an extended smram space of up to 1 mb can be defined in the address range just below the top of memory. the size of the smram space is determined by the tseg_sz value in the esmramc register. when the extended smram space is enabled, non-smm processor accesses and all pci-initiated accesses in this range are terminated on the external pci bus. when smm is enabled the amount of memory available to the system is equal to the amount of physical dram minus the value indicated by the tseg_sz bits. 6.2.2.3 pci memory address range (top of main memory to 4 gb) the address range from the top of main dram to 4 gb (top of physical memory space) is normally mapped to the external pci bus, with some exceptions mapped to the x-bus. the two sub-ranges within the pci memory address range are defined as the high bios address range. 6.2.2.4 high bios area (ffc0_0000h - ffff_ffffh) the top 4 mb of the extended memory region is reserved for system bios (high bios), extended bios for pci devices, and the a20 alias of the system bios. the processor begins execution from the high bios after reset. except for the top 512 kb, which is always mapped to the x-bus, this region can be mapped to either the x-bus or the external pci bus. the upper subset of this region aliases to the 256 kb area just below 16 mb . the actual address space required for the bios is less than 4 mb, but the minimum processor mtrr range for this region is 2 mb, so the full 2 mb must be considered. 6.3 system management mode (smm) memory range main memory can be used as system management ram (smram) by enabling the system management mode. two smram options are supported: compatible smram (c_smram) and extended smram (e_smram). system management ram (smram) space provides a memory area that is available for the smi handlers and code and data storage. this memory resource is normally hidden from the system os so that the processor has immediate access to this memory space upon entry to smm. only the processor can access smm space. three options for smram locations are provided:  below 1-mb option that supports compatible smi handlers.
82443MX pciset 45  above 1-mb option that allows new smi handlers to execute with write-back cacheable smram.  optional larger write-back cacheable t_seg area, from 128 kb to 1 mb in size, above 1 mbyte. this area is located just below the top of main memory. both of the above 1-mbyte solutions require changes to compatible smram handler code to properly execute above 1 mbyte. 6.4 memory shadowing any block of memory that can be designated as read-only or write-only can be shadowed into main memory. typically this is done to allow rom code to execute more rapidly out of main dram. to achieve this, rom is designated read-only during the copy process while at the same time dram is designated write- only. after copying, the dram is designated read-only so that rom is shadowed. processor bus transactions are routed accordingly. 6.5 decode rules and cross-bridge address mapping the address map described above, with the exception of smram, applies globally to accesses arriving on either the host bus or the external pci bus. accesses initiated from any of the other peripheral buses, other than the host bus and the external pci bus (e.g., usb, ide), are only allowed to access main memory, and must not attempt to access any other memory space on or behind the 440mx. 6.5.1 pci interface memory decode rules all memory read and write accesses are accepted from the external pci bus that are targeted to main dram. pci accesses that fall elsewhere within the pci memory range will not be claimed. this implies that external pci devices cannot access bios memory on the x-bus. 6.5.2 legacy vga range the legacy vga memory range a0000h-bffffh is always mapped to the external pci bus in normal mode. (in smm, it is mapped to main memory.) 6.6 i/o address space for all processor-initiated i/o accesses, cycles are internally terminated, or bus cycles are generated on the internal pci bus. the cycles generated on the internal pci bus can be one of two types:  pci configuration cycles  pci i/o cycles for the purpose of converting i/o cycles to pci configuration cycles, two internal registers are used. these registers are located in the processor i/o space, the configuration address register (config_address) and the configuration data register (config_data). these registers are used to implement the pci configuration space access mechanism as described in the pci configuration section. if the pci configuration register accessed via the i/o space is internal to the 440mx north bridge/cluster, the cycle will not be generated on the internal pci bus.) if the pci configuration register accessed is not internal to the 440mx north bridge/cluster, the cycle will be generated on the internal pci bus and also broadcast to the external pci bus.
82443MX pciset 46 cycles other than those intended to be converted to pci configuration cycles are sent to the internal pci bus, broadcast as i/o cycles to the external pci bus, and positively or subtractively decoded by the 440mx south bridge/cluster for i/o regions residing in or behind the 440mx south bridge/cluster. the processor allows 64k+3 bytes of i/o addressable space to be addressed. processor i/o addresses are propagated without any translation onto the destination bus except for i/o to i/o-to-configuration space conversions. this provides addressability for 64k+3 byte locations. note that the upper 3 three locations can be accessed only during i/o address wrap-around when the processor bus a16# address signal is asserted. a16# is asserted on the processor bus whenever an i/o access is made to the 4four- byte range starting from address 0fffdh, 0fffeh, or 0ffffh. a16# is also asserted when an i/o access is made to the 2two- byte range starting from address 0ffffh. i/o write cycles are not posted. the i/o map is divided into fixed and variable ranges. fixed ranges cannot be moved, but in some cases can be disabled. variable ranges can be moved and can also be disabled. 6.6.1 fixed i/o address ranges table 34 shows the fixed i/o decode ranges positively decoded by the 440mx south bridge/cluster. if a pci master targets fixed i/o ranges, they are positively decoded at medium speed. address ranges that are not listed or are marked reserved are not positively decoded (unless assigned to one of the variable ranges) but may be subtractively decoded if subtractive decode mode is enabled. table 34. fixed i/o ranges decoded by the 440mx i/o address alias register name/function bus master access forwarded to isa/eio? default value reg. type 000h 010h dma base/current address (ch0) cpu / pci never xxxxh r/w 001h 011h dma base/current byte/word (ch0) cpu / pci never xxxxh r/w 002h 012h dma base/current address (ch1) cpu / pci never xxxxh r/w 003h 013h dma base/current byte/word (ch1) cpu / pci never xxxxh r/w 004h 014h dma base/current address (ch2) cpu / pci never xxxxh r/w 005h 015h dma base/current byte/word (ch2) cpu / pci never xxxxh r/w 006h 016h dma base/current address (ch3) cpu / pci never xxxxh r/w 007h 017h dma base/current byte/word (ch3) cpu / pci never xxxxh r/w 008h 018h dma command register (ch 0-3) cpu / pci never 00h wo 008h 018h dma status register (ch 0-3) cpu / pci never 00h ro 009h 019h dma request register (ch 0-3) cpu / pci never 000000xx wo 00ah 01ah mask register - write single mask (ch 0-3) cpu / pci never 000001xx wo 00bh 01bh dma channel mode register (ch 0-3) cpu / pci never 000000xx wo
82443MX pciset 47 i/o address alias register name/function bus master access forwarded to isa/eio? default value reg. type 00ch 01ch dma clear byte pointer (ch 0-3) cpu / pci never xxh wo 00dh 01dh dma master clear register. (ch 0-3) cpu / pci never xxh wo 00eh 01eh dma clear mask register (ch 0-3) cpu / pci never xxh wo 00fh 01fh write all mask (ch 0-3) cpu / pci never 01h r/w 020h 024, 028, 02c, 030, 034, 038, 03c int1 control register cpu / pci never r/w 021h 025, 029, 02d, 031, 035, 039, 03d int1 mask registers cpu / pci never r/w 040h 050h timer/counter 1 - counter 0 count cpu / pci never r/w 041h 051h timer/counter 1 - counter 1 count cpu / pci never r/w 042h 052h timer/counter 1 - counter 2 count cpu / pci never r/w 043h 053h timer/counter 1 - cmnd mode cpu / pci never w/o 060h 062h kbc input buffer cpu / pci if enabled wo 060h 062h kbc output buffer cpu / pci if enabled ro 060h 062h reset x-bus irq12 and irq1 cpu / pci never n/a ro 061h 063, 065, 067h nmi status and control register cpu / pci never 00h r/w 62h, 66h microcontroller chip select cpu / pci if enabled r/w 064h kbc status register cpu / pci if enabled wo 064h kbc command register cpu / pci if enabled ro 070h 072, 074, 076h nmi mask (bit 7) cpu / pci if rtc disabled and not on pci wo 070h 072, 074, 076h rtc index register (not aliased to 072h if extended ram enabled) cpu / pci if rtc disabled and not on pci r/w 071h 073, 075, 077h rtc data register (not aliased to 73h if extended ram enabled) cpu / pci if rtc disabled and not on pci r/w 072h rtc extended index register cpu / pci if enabled r/w
82443MX pciset 48 i/o address alias register name/function bus master access forwarded to isa/eio? default value reg. type 073h rtc extended data register cpu / pci if enabled r/w 080h 090h dma1 page register (reserved) cpu / pci writes forwarded alias writes forwarded if enabled r/w 081h 091h dma1 memory low page (ch2) cpu / pci never xxh r/w 082h dma1 memory low page (ch3) cpu / pci never xxh r/w 083h 093h dma1 memory low page (ch1) cpu / pci never xxh r/w 084h 094h dma1 page register (reserved) cpu / pci writes forwarded alias writes forwarded if enabled r/w 085h 095h dma1 page register (reserved) cpu / pci writes forwarded alias writes forwarded if enabled r/w 086h 096h dma1 page register (reserved) cpu / pci writes forwarded alias writes forwarded if enabled r/w 087h 097h dma1 memory low page register (ch0) cpu / pci never xxh r/w 088h 098h dma1 page register (reserved) cpu / pci writes forwarded alias writes forwarded if enabled r/w 089h 099h dma1 memory low page (ch6) cpu / pci never xxh r/w 08ah 09ah dma1 memory low page (ch7) cpu / pci never xxh r/w 08bh 09bh dma1 memory low page (ch5) cpu / pci never xxh r/w 08ch 09ch dma1 page register (reserved) cpu / pci writes forwarded alias writes r/w
82443MX pciset 49 i/o address alias register name/function bus master access forwarded to isa/eio? default value reg. type forwarded if enabled 08dh 09dh dma1 page register (reserved) cpu / pci writes forwarded r/w 08eh 09eh dma1 page register (reserved) cpu / pci writes forwarded alias writes forwarded if enabled r/w 08fh 09fh dma1 low page register refresh cpu / pci never r/w 92h fast a20 and init register cpu / pci never 00h r/w 0a0h 0a4, 0a8, 0ac, 0b0, 0b4, 0b8, 0bch int2 control register cpu / pci never r/w 0a1h 0a5, 0a9, 0ad, 0b1, 0b5, 0b9, 0bdh int2 1 mask registers cpu / pci never r/w 0b2h advanced power management control port cpu / pci never 00h r/w 0b3h advanced power management status port cpu / pci never 00h r/w 0c0h 0c1h dma2 base/current address (ch4) cpu / pci never xxxxh r/w 0c2h 0c3h dma2 base/current byte/word ch4 cpu / pci never xxxxh r/w 0c4h 0c5h dma2 base/current address (ch5) cpu / pci never xxxxh r/w 0c6h 0c7h dma2 base/current byte/word ch5 cpu / pci never xxxxh r/w 0c8h 0c9h dma2 base/current address (ch6) cpu / pci never xxxxh r/w 0cah 0cbh dma2 base/current byte/word ch6 cpu / pci never xxxxh r/w 0cch 0cdh dma2 base/current address ch7 cpu / pci never xxxxh r/w 0ceh 0cfh dma2 base/current byte/word ch7 cpu / pci never xxxxh r/w 0d0h 0d1h dma2 command register (ch 4-7) cpu / pci never 00h wo 0d0h 0d1h dma2 status register (ch 4-7) cpu / pci never 00h ro 0d2h 0d3h dma2 request register (ch 4-7) cpu / pci never 000000xx wo
82443MX pciset 50 i/o address alias register name/function bus master access forwarded to isa/eio? default value reg. type 0d4h 0d5h dma2 write single mask (ch 4-7) cpu / pci never 000001xx wo 0d6h 0d7h dma2 channel mode reg (ch 4-7) cpu / pci never 000000xx wo 0d8h 0d9h dma2 clear byte pointer (ch 4-7) cpu / pci never xxh wo 0dah 0dbh dma2 master clear reg. (ch 4-7) cpu / pci never xxh wo 0dch 0ddh dma2 clear mask register (ch 4-7) cpu / pci never xxh wo 0deh 0dfh dma2 write all mask (ch 4-7) cpu / pci never 01h r/w 0f0h coprocessor error register cpu / pci always n/a wo 170h - 177h ide secondary command block (note 1) cpu / pci never n/a r/w 1f0h - 1f7h ide primary command block cpu / pci never n/a r/w 200h- 207h game port cpu / pci if enabled n/a r/w 279h isa pnp address cpu / pci if enabled n/a r/w 376h ide secondary control block cpu / pci never n/a r/w 388-38bh adlib fm synthesis cpu / pci if enabled n/a r/w 3f6h ide primary control block cpu / pci never n/a r/w 4d0h edge/level triggered reg (int ctrl 1) never 00h r/w 4d1h edge/level triggered reg (int ctrl 2) never 00h r/w a79h isa pnp address cpu / pci if enabled n/a r/w cf9h reset control register never 00h r/w note: 1. the 440mx claims secondary ide addresses even though no secondary channel is physically available. 6.6.2 variable i/o decode ranges table 35 shows the variable i/o decode ranges, which are set using base address registers (bars) or other configuration bits in the various configuration spaces. the pnp software (pci or acpi) can set and adjust these values. when a detected cycle is positively decoded, if it is an x-bus device response, then the cycle is forwarded to the x-bus i/f.
82443MX pciset 51 warning: the variable i/o ranges should not be set to conflict with the fixed i/o ranges. unpredictable results may occur if the configuration software allows any i/o range conflicts to happen. hardware checks are not performed for programming conflicts. table 35. variable i/o decode ranges (available i/o space is 0 - 64kb) range name mappable size (bytes) target ide anywhere in 64k i/o space 16 ide unit usb anywhere in 64k i/o space 32 usb unit smbus anywhere in 64k i/o space 16 smbus unit ac97 mixer anywhere in 64k i/o space 256 ac97 unit ac97 bus master (audio) anywhere in 64k i/o space 64 ac97 unit ac97 bus master (modem) anywhere in 64k i/o space 64 ac97 unit ac97 modem anywhere in 64k i/o space 128 ac97 unit gpio anywhere in 64k i/o space 256 gpio unit parallel port 1 of 3 ranges in 64k i/o space 8 x-bus peripheral serial ports 1 & 2 1 of 8 ranges in 64k i/o space 8 x-bus peripheral floppy disk controller 1 of 2 ranges in 64k i/o space 8 x-bus peripheral midi 1 of 2 ranges in 64k i/o space 2 x-bus peripheral mss 1 of 4 ranges in 64k i/o space 8 x-bus peripheral soundblaster 1 of 4 ranges in 64k i/o space 32 x-bus peripheral x-bus programmable chip select decode ranges [0:1] anywhere in 64k i/o space 1-16 x-bus peripheral figure 4 shows how the 440mx uses the pci configuration space.
82443MX pciset 52 cpu pci configuration window host-pci bridge, dram control bus #0 dev. #0 pci- peripherals bus #0 dev. #7 function 0: pci to x-bus bridge function 1: ide function 2: usb function 1: ac'97 audio function 2: ac'97 modem function 3: power management, smbus platform pci confi g uration pci0 (physical- bus #0) pci devices pci devices function 0: dma function 0: pci to x-bus bridge, acpi figure 4. pci configuration space block diagram
82443MX pciset 53 7. functional description 7.1 mobile celeron? processor / pentium ? ii processor host interface 7.1.1 overview the host interface is optimized to support the mobile celeron processor or the pentium ii processor at a 66 mhz bus clock frequency. the 440mx implements the host address, control, and data bus interfaces within a single device. host bus addresses are decoded for accesses to main memory, pci memory, pci i/o, and pci configuration space. pipelined addressing capability is utilized to improve overall system performance. 7.1.2 host bus device support the 440mx recognizes and supports a large subset of the transaction types that are defined for the mobile celeron processor / pentium ii processor bus interface. however, each transaction type has a multitude of response types, some of which are not supported by this controller. all transactions are processed in the order received on the processor bus. table 36 summarizes the transactions supported. table 36. host bus transactions supported transaction reqa[4:0]# reqb[4:0]# support deferred reply 0 0 0 0 0 x x x x x a deferred reply is initiated for a previously deferred transaction. reserved 0 0 0 0 1 x x x x x reserved interrupt acknowledge 0 1 0 0 0 0 0 0 0 0 interrupt acknowledge cycles are forwarded to the internal pci bus. special transactions 0 1 0 0 0 0 0 0 0 1 see table 38. reserved 0 1 0 0 0 0 0 0 1 x reserved reserved 0 1 0 0 0 0 0 1 x x reserved branch trace message 0 1 0 0 1 0 0 0 0 0 a branch trace message is terminated without latching data. reserved 0 1 0 0 1 0 0 0 0 1 reserved reserved 0 1 0 0 1 0 0 0 1 x reserved reserved 0 1 0 0 1 0 0 1 x x reserved i/o read 1 0 0 0 0 0 0 x len# i/o read cycles are forwarded to the pci bus. i/o cycles in the north bridge / cluster configuration space are not forwarded to the pci bus. i/o write 1 0 0 0 1 0 0 x len# i/o write cycles are forwarded to the pci bus. i/o cycles in the north bridge / cluster configuration space are not forwarded to the pci bus.
82443MX pciset 54 transaction reqa[4:0]# reqb[4:0]# support reserved 1 1 0 0 x 0 0 x x x reserved memory read & invalidate 0 0 0 1 0 0 0 x len# host initiated memory read cycles are forwarded to dram or the pci bus. an mri cycle is initiated for a pci-initiated write cycle to dram. reserved 0 0 0 1 1 0 0 x len# reserved memory code read 0 0 1 0 0 0 0 x len# memory code read cycles are forwarded to dram or pci. memory data read 0 0 1 1 0 0 0 x len# host initiated memory read cycles are forwarded to dram or the pci bus. a memory read cycle is initiated for a pci-initiated read cycle to dram. memory write (no retry) 0 0 1 0 1 0 0 x len# this memory write is a writeback cycle and cannot be retried. the write is forwarded to dram. memory write (can be retried) 0 0 1 1 1 0 0 x len# the standard memory write cycle is forwarded to dram or pci. notes: for memory cycles, reqa[4:3]# = asz#. the 440mx only supports asz# = 00 (32-bit address). reqb[4:3]# = dsz#. for the mobile celeron processor / pentium ii processor, dsz# = 00 (64-bit data bus size). len# = data transfer length as follows: len# data length 00 <= 8 bytes (be[7:0]# specify granularity) 01 length = 16 bytes be[7:0]# all active (not supported) 10 length = 32 bytes be[7:0]# all active 11 reserved table 37 shows the supported host bus responses. table 37. host bus responses supported rs2# rs1# rs0# description 440mx support 00 0idle 0 0 1 retry response this response is generated if an access is made to a resource that cannot be accessed by the processor at that time and the logic must avoid deadlock. pci-directed reads, writes, and dram locked reads can be retried. 0 1 0 deferred response this response can be returned for all transactions that can be executed out of order. pci-directed reads (memory, i/o and interrupt acknowledge) and writes (i/o only) can be deferred. 0 1 1 reserved reserved 1 0 0 hard failure not supported. 1 0 1 no data response this response is for transactions where the data has been transferred or for transactions where no data is
82443MX pciset 55 rs2# rs1# rs0# description 440mx support transferred. writes and zero length reads receive this response. 1 1 0 implicit writeback this response is generated for transactions that hit a modified cache line. 1 1 1 normal data response this response is for transactions where data accompanies the response phase. reads receive this response. 7.1.3 special cycles a special cycle is defined when reqa[4:0]=01000 and reqb[4:0]=xx001. the first address phase, aa[35:3]# is undefined and can be driven to any value. the second address phase, ab[15:8]# defines the type of special cycle issued by the processor. table 38 specifies the cycle type and definition, as well as the action by the 440mx when the corresponding cycles are identified. table 38. special cycle transactions be[7:0}# special cycle type action taken 0000 0000 nop this transaction has no effect. 0000 0001 shutdown this transaction is issued when an agent detects a severe software error that prevents further processing. this cycle is claimed by the 440mx, which issues a shutdown special cycle on the pci bus. this cycle is retired on the cpu bus after it is terminated on the pci via a master abort mechanism. 0000 0010 flush this transaction is issued when an agent has invalidated its internal caches without writing back any modified lines. the 440mx claims this cycle and retires it. 0000 0011 halt this transaction is issued when an agent executes an hlt instruction and stops program execution. this cycle is claimed by the 440mx and propagated to pci as a special halt cycle. this cycle is retired on the cpu bus after it is terminated on the pci via a master abort mechanism. 0000 0100 sync this transaction is issued when an agent has written back all modified lines and has invalidated its internal caches. the 440mx claims this cycle and retires it. 0000 0101 flush acknowledg e this transaction is issued when an agent has completed a cache sync and flush operation in response to an earlier flush# signal assertion. the 440mx claims this cycle and retires it. 0000 0110 stop clock acknowledg e this transaction is issued when an agent enters stop clock mode. this cycle is claimed by the 440mx and propagated to the pci as a special stop grant cycle. this cycle is completed on the cpu bus after it is terminated on the pci via a master abort mechanism.
82443MX pciset 56 be[7:0}# special cycle type action taken 0000 0111 smi acknowledg e this transaction is first issued when an agent enters system management mode (smm). ab[7]# is also set at this entry point. all subsequent transactions from the cpu with ab[7]# set are treated by the 440mx as accesses to the smm space. no corresponding cycle is propagated to the pci. to exit smm, the cpu issues another one of these cycles with the ab[7]# bit de-asserted. the smm space access is closed by the 440mx at this point. all others reserved 7.1.4 symmetric multiprocessor (smp) configuration symmetrical multi-processor configurations are not supported. 7.1.5 in-order queue pipelining the interface to the cpu bus includes a four deep in-order queue to track pipelined bus transactions. when the in-order queue is nearly full, the cpu bus pipeline is halted by asserting bnr#. bnr# is asserted until the in-order queue begins to drain. 7.1.6 frame buffer memory support (uswc) to allow for high-speed write capability for graphics, the pentium ii processor family introduced the uswc (uncacheable, speculative, write-combining) memory type. the uswc memory type provides a write- combining buffering mechanism for write operations. a high percentage of graphics transactions are writes to the memory-mapped graphics region, normally known as the linear frame buffer. reads and writes to uswc are non-cached and can have no side effects. in the case of graphics, current 32-bit drivers (without modifications) would use partial write protocol to update the frame buffer. the highest performance write transaction on the cpu bus is the line write. by combining the several back-to-back partial write transactions (internal to the cpu) into a line write transaction on the cpu bus, the performance of frame buffer accesses would be greatly improved. to this end, the cpu supports the uswc memory. writes to uswc memory can be buffered and combined in the processor's write-combining buffers (wcb). the wcb is flushed after executing a serializing, locked, i/o instruction, or when the wcb is full (32 bytes). to extend this capability to the current drivers, it is necessary to set the linear frame buffer address range to a uswc memory type, which can be done by programming the mtrr registers in the cpu. if the number of bytes in the wcb is < 32 then a series of  8 byte writes are performed upon wcb flushing. the 440mx further optimizes this by providing write combining for cpu-to-pci write transactions. if the target of a cpu write is the pci memory, then the data is combined and sent to the pci bus as a single write burst. the uswc dram-targeted writes are handled as regular dram writes. note that the application of the uswc memory attribute is not limited only to the frame buffer support. the 440mx implements write combining for any cpu-to-pci posted write.
82443MX pciset 57 7.1.7 cpu sideband interface this section describes each of the sideband signals that interface between the 440mx and the processor. the 440mx interfaces to the mobile processor with the following seven outputs:  a20m#  ferr# / ignne#  init#  intr  nmi  smi#  stpclk# outputs to the cpu use open drain buffers, which are pulled up at the system level to the cpu voltage. one input, ferr#, from the cpu has special buffer requirements for the different voltage levels. the v il threshold must be compatible with cpus that do not drive the signal above 1.8v. 7.1.7.1 a20m# the a20m# signal is active (low) when both of the following conditions are true:  the alt_a20_gate bit (bit 1 of port92 register) is a 0.  the a20gate input signal is a 0. the a20gate input signal is expected to be generated by the external microcontroller (kbc). 7.1.7.2 ferr# / ignne# (coprocessor error) the 440mx supports the coprocessor error function with the ferr#/ignne# pins. the function is enabled via the coproc_err_en bit (device 7:function 0, offset 4e, bit 5). ferr# is tied directly to the coprocessor error signal of the cpu. as shown in figure 5, if ferr# is driven active by the cpu, irq13 goes active (internally). when it detects a write to the coproc_err register, the 440mx negates the internal irq13 and drives ignne# active. ignne# remains active until ferr# is driven inactive. ignne# is never driven active unless ferr# is active. if coproc_err_en is not set, then asserting ferr# does not generate an internal irq13 and a write to f0h does not generate ignne#.
82443MX pciset 58 ferr# internal irq13 i/o write to f0h ignne# figure 5. coprocessor error timing diagram 7.1.7.3 init# the init# signal is active (driven low) based on any one of several events as shown in table 39. when any of these events occur, init# is driven low for 16 pci clocks and then released (and pulled high by an external pull-up resistor). table 39. events causing init# active event comment shutdown special cycle from cpu observed. port92 write, where init_now (bit 0) transitions from a 0 to a 1. portcf9 write, where rst_cpu ( bit 2 ) was a 0 and sys_rst (bit 1) transitions from 0 to 1. rcin# input signal goes low. rcin# is expected to be driven by the external microcontroller (kbc). 0 to 1 transition on rcin# must occur before the 440mx arms init# to be generated again. 7.1.7.4 interrupt signals the behavior of the intr signal is described in section 7.10.1 of this document. 7.1.7.5 nmi non-maskable interrupts (nmis) can be generated when either serr# or iochk# is asserted. 7.1.7.6 smi# smi# is an active low output synchronous to pciclk that is asserted by the 440mx in response to one of many enabled hardware or software events. 7.1.7.7 stpclk# this active-low, open-drain signal is controlled by the power management.
82443MX pciset 59 7.2 memory interface 7.2.1 dram interface 7.2.1.1 dram interface overview the 440mx integrates a main memory dram controller that supports a 64-bit sdram array. the 440mx generates the cs#, dqm, scas#, sras#, sclk, we#, cke and multiplexed addresses, ma[13,(12:11)#,10,(9:0)#] for the dram array. for cpu/pci to dram cycles, the address and data flows through the 440mx. the 440mxs dram interface operates on a clock that is synchronous to the cpus fsb clock at 66 mhz. the dram controller interface is fully configurable through a set of control registers. the 440mx supports industry standard 64-bit wide sdram dimm modules. the 14 multiplexed address lines, ma[13:0], allow the 440mx to support 1m, 2m, 4m, 8m, and 16m x64 dimms. the 440mx has 4 cs# lines enabling the support of up to four 64-bit rows of dram in two dimm modules. for write operations of less than a qword in size, the 440mx performs a byte-wide write with dqms. the 440mx targets 66 mhz sdram and supports both single and double-sided dimms. the 440mx provides refresh functionality with programmable rate (normal dram rate is 1 refresh/15.6  s). additionally, the 440mx provides a seven-deep refresh queue. the 440mx can be configured via the paging policy register to keep multiple pages open within the memory array. pages can be kept open in all rows of memory. when 4-bank sdram devices (64mb technology) are used for a particular row, up to 4 pages can be kept open within that row. when using 2-bank sdram devices in a particular row, up to 2 pages can be kept open within that row. the dram interface of the 440mx is configured by the sdram control register, the nbxcfg register bits, and the four dram row boundary (drb) registers. the four drb registers define the size of each row in the memory array, enabling the 440mx to assert the proper cs# for accesses to the array. 7.2.2 dram organization and configuration the 440mx supports 64-bit dram configurations. in the following discussion, the term row refers to a set of memory devices that are simultaneously selected by one cs#. the 440mx supports a maximum of 4 rows of sdram memory. a row may be composed of discrete dram devices, single-sided or double-sided dimms. the dram interface consists of the following pins:  ma[13,(12:11)#,10,(9:0)#]  md[63:0]  dqm[7:0]  sras#  scas#  we#  cs[3:0]#  cke[3:0] one cs# line is provided for each row. the sras#, scas# and we# drive up to 4 rows of sdram. most pins utilize programmable strength output buffers. when a row contains 16-mb sdrams, ma11# functions as a bank select line. when a row contains 64-mb or 128-mb sdrams, ma[12:11]# function as bank addresses (ba[1:0], or bank selects).
82443MX pciset 60 dimms may be populated in any order, i.e., any combination of rows may be populated. table 40 lists some possible dimm socket configurations along with their corresponding drb programming. table 40. sample of possible options for 6 row/3 dimm configurations total memory size dimm0 dimm1 drb0 drb1 drb2 drb3 16 mb 2mx64/s 0 02h 02h 02h 02h 16 mb 0 2mx64/d 00h 00h 01h 02h 16 mb 1mx64/s 1mx64/s 01h 01h 02h 02h 24 mb 2mx64/d 1mx64/s 01h 02h 03h 03h 24 mb 1mx64/s 2mx64/s 01h 01h 03h 03h 32 mb 4mx64/s 0 04h 04h 04h 04h 32 mb 0 4mx64/s 00h 00h 04h 04h 32 mb 2mx64/d 2mx64/d 01h 02h 03h 04h 40 mb 4mx64/s 1mx64/s 04h 04h 05h 05h 40 mb 1mx64/s 4mx64/s 01h 01h 05h 05h 48 mb 4mx64/s 2mx64/d 04h 04h 05h 06h 48 mb 2mx64/s 4mx64/s 02h 02h 06h 06h 48 mb 2mx64/d 4mx64/s 01h 02h 06h 06h 64 mb 8mx64/d 0 04h 08h 08h 08h 64 mb 0 8mx64/d 00h 00h 04h 08h 64 mb 4mx64/s 4mx64/s 04h 04h 08h 08h 72 mb 8mx64/d 1mx64/s 04h 08h 09h 09h 72 mb 1mx64/s 8mx64/d 01h 01h 05h 09h 80 mb 8mx64/d 2mx64/d 04h 08h 09h 0ah 80 mb 2mx64/s 8mx64/d 02h 02h 06h 0ah 96 mb 8mx64/d 4mx64/s 04h 08h 0ch 0ch 96 mb 4mx64/s 8mx64/d 04h 04h 08h 0ch 128 mb 8mx64/d 8mx64/d 04h 08h 0ch 10h 256 mb 16mx64/d 16mx64/d 08h 10h 18h 20h note: "s" denotes single-sided dimms and "d" denotes double-sided dimms.
82443MX pciset 61 figure 6 depicts the 440mx connections for a two-dimm sdram memory array. cs[1:0]# cs[3:2]# sras# scas# dqm[7:0] we# cke[1:0]# cke[3:2]# ma[13,12#, 11#,10,(9:0)#] md[63:0] clk[3:0] clk[7:4] dimm0 dimm1 smb_data smb_clk figure 6. dimm configuration with fet switches 7.2.2.1 configuration mechanism for dimms detection of the dram type installed on the dimm is supported via the serial presence detect mechanism as defined in the jedec 168-pin dimm standard. this standard uses the scl (smb_clk), sda (smb_data) and sa[2:0] pins on the dimms to detect the type and size of the installed dimms. no special programmable modes are provided for detecting the size and type of memory installed. type and size detection must be done via the serial presence detection pins. 7.2.2.1.1 memory detection and initialization the dram registers must be initialized before any cycles to the memory interface can be supported. detection of memory size is done via the system management bus (smbus). this two-wire bus is used to extract the dram type and size information from the serial presence detect port on the dram dimms. dram dimms contain a five-pin serial presence detect interface, including scl (serial clock), sda (serial data) and sa[2:0]. each device on the smbus bus has a seven-bit address. for the dram dimms, the upper four bits are fixed at 1010. the lower three bits are strapped on the sa[2:0] pins. scl and sda are connected directly to the smbus. thus, data is read from the serial presence detect port on the dimms via a
82443MX pciset 62 series of smbus i/o cycles. to properly configure the memory interface, the bios uses this data to determine the memory size of each of the four rows. 7.2.2.1.2 smbus configuration before accessing the information from the dimms, the smbus host interface must be initialized. this is done via two registers mapped to pci configuration space device #7, function #7. all smbus accesses are done through i/o cycles. it is desirable to make the i/o base address programmable to avoid any conflicts with existing i/o mapped devices in the system. the i/o address is programmed through the 32-bit smbus base address register at location 90h, device #7, function #7. bits 31:16 of this register are reserved. bits 15:4 are used to select the 16-bit base i/o address of the smbus host controller. bits 3:1 are reserved and bit 0 is hard-wired to 1 indicating that the smbus host controller is always i/o mapped. the second register to be configured is the smbus host configuration register located at d2h, device #7, function #7. bits 7:4 of this register are reserved. bits 3:1 are used to assign an interrupt to the smbus host controller. irq9 or smi# may be selected. the smbus host interface is enabled upon setting bit 0 of this register to 1. 7.2.2.1.3 accessing the serial presence detect ports each device on the smbus has a unique seven-bit address. the dram dimms have the upper four bits of this address hard-wired as 1010. the remaining three bits are strapped for each dimm on the sa[2:0] pins. for example, to support two dimms (four rows of memory), the sa[2:0] lines may be strapped to 000 and 001. thus, an smbus cycle with target address 1010000 addresses the lower order dimm. each dimm contains an eeprom with up to 256 bytes of accessible data. the bios can read this data from the serial presence detect ports to determine the type, size and any required attributes of each row of memory. once the smbus host controller is initialized and enabled, accessing the serial presence detect ports can be done through a sequence of i/o reads and writes to i/o space registers defined by the smbus base i/o address (see section 7.2.2.1.2). 7.2.2.1.4 dram register programming this section provides an overview of how the serial presence detect ports on the dimms obtain the required information to program the dram registers. the serial presence detect ports are used to determine refresh rate, ma and md buffer strength, sdram timings, row sizes and row page sizes. table 41 lists a subset of the data available through the on-board serial presence detect rom on each dimm. table 41. data bytes on dimm used for programming dram registers byte function 2 memory type ( sdram) 3 # row addresses, not counting bank addresses 4 # column addresses 5 # banks of dram (single- or double-sided dimm) 11 no ecc 12 refresh rate
82443MX pciset 63 byte function 17 # banks on each sdram device 36-41 access time from clock for cas# latency 1 through 7 42 data width of sdram components these bytes collectively provide enough data to program the dram registers. for example, to program the drb (dram row boundary) registers, the size of each row must be determined. the number of row addresses (byte 3) plus the number of column addresses (byte 4) plus the number of banks on each sdram device (byte 17) collectively determines the total address depth of a particular row of sdram. since a row is always 64 data bits wide, the size of the row is easily determined for programming the drb registers. once the type of dram has been detected, this information must then be programmed into the dram row boundary registers. the 440mx uses the dram row type information in conjunction with the dram timings set in the dram timing register to optimally configure dram accesses. 7.2.3 sdram cycle encoding table 42 through table 44 show the sdram cycle encoding using cs#, sras#, scas#, we# and bank select. table 42. command truth table function symbol cke n-1 cke n cs# sras# scas# we# a11 a10 a9-a0 device deselect dsel hxh x x xxxx no operation nop h x l h h h x x x read read hxlh lhvlv read w/ auto precharge readap h x l h l h v h v write writ hxl h l lvlv write w/ auto precharge writeap h x l h l l v h v bank activate act h x l l h h v v v precharge select bank pre h x l l h l v l x precharge all banks pall h x l l h l x h x auto refresh cbr h h l l l h x x x self refresh entry from idle slfrsh h l l l l h x x x self refresh exit slfrshxlhh x x xxxx power down entry from idle pwrdnhlx x x xxxx power down exit pwrdnx l h x x x xxxx
82443MX pciset 64 function symbol cke n-1 cke n cs# sras# scas# we# a11 a10 a9-a0 mode register set mrs h x l l l l l l v table 43. dqm truth table function cke n-1 cke n dqm u dqm l data write/output enable h x l l data mask/output disable h x h h upper byte write enable/lower byte mask h x l h lower byte write enable/high byte mask h x h l note: h = high level, l = low level, x = dont care, v = valid data input table 44. operative command table current state cs# sras # scas # we# address command action notes idle hxxxx dsel nop or power down1 lhhhx nop nop or power down1 l h l h ba,ca,a10 read/readap illegal 2 l h l l ba,ca,a10 writ/writeap illegal 2 l l h h ba,ra act row active l l h l ba,a10 pre/pall nop l l l h x cbr/self refresh or self refresh 3 llllop-codemrs m ode register access row activehxxxx dsel nop lhhhx nop nop l h l h ba,ca,a10 read/readap begin read: optional ap 4 l h l l ba,ca,a10 writ/writeap begin write: optional ap 4 l l h h ba,ra act illegal 2 l l h l ba,a10 pre/pall precharge 5 l l l h x cbr/self illegal 11 llllop-codemrs illegal 11 read hxxxx dsel conti nue burst to end ->
82443MX pciset 65 current state cs# sras # scas # we# address command action notes row active lhhhx nop conti nue burst to end -> row active l h l h ba,ca,a10 read/readap term burst, new read:optional ap 6 l h l l ba,ca,a10 writ/writeap term burst, start write:optional ap 6,7 l l h h ba,ra act illegal 2 l l h l ba,a10 pre/pall term burst, precharge l l l h x cbr/self illegal 11 llllopcodemrs illegal 11 write h x x xx x dsel continue burst to end - > write recovering lhhhx nop conti nue burst to end - > write recovering l h l h ba,ca,a10 read/readap term burst, start read: optional ap 6,7 l h l l ba,ca,a10 writ/writeap term burst, new write: optional ap 6 l l h h ba,ra act illegal 2 l l h l ba,a10 pre/pall term burst precharging 8 l l l h x cbr/self illegal 11 llllop codemrs illegal 11 read with auto hxxxx dsel conti nue burst to end - > precharging prechargelhhhx nop conti nue burst to end - > precharging l h l h ba,ca,a10 read/readap illegal 10 l h l l ba,ca,a10 writ/writeap illegal 10 l l h h ba,ra act illegal 2,10 l l h l ba,a10 pre/pall illegal 2,10 l l l h x cbr/self illegal 11 llllopcodemrs illegal 11
82443MX pciset 66 current state cs# sras # scas # we# address command action notes write with auto precharge hxxxx dsel conti nue burst to end -> write recovering with auto precharge lhhhx nop conti nue burst to end -> write recovering with auto precharge l h l h ba,ca,a10 read/readap illegal 10 l h l l ba,ca,a10 writ/writeap illegal 10 l l h h ba,ra act illegal 2,10 l l h l ba,a10 pre/pall illegal 2,10 l l l h x cbr/self illegal 11 llllopcodemrs illegal 11 prechargin g hxxxx dsel nop lhhhx nop nop l h l h ba,ca,a10 read/readap illegal 2,10 l h l l ba,ca,a10 writ/writeap illegal 2,10 l l h h ba,ra act illegal 2,10 l l h l ba,a10 pre/pall nop l l l h x cbr/self illegal 11 llllop codemrs illegal 11 row hxxxx dsel nop activatinglhhhx nop nop l h l h ba,ca,a10 read/readap illegal 2,10 l h l l ba,ca,a10 writ/writeap illegal 2,10 l l h h ba,ra act illegal 2,9,10 l l h l ba,a10 pre/pall illegal 2,10 l l l h x cbr/self illegal 11 llllopcodemrs illegal 11 write hxxxx dsel nop recoveringlhhhx nop nop
82443MX pciset 67 current state cs# sras # scas # we# address command action notes l h l h ba,ca,a10 read/readap start read, optional ap 7 l h l l ba,ca,a10 writ/writeap new write, optional ap l l h h ba,ra act illegal 2,10 l l h l ba,a10 pre/pall illegal 2,11 l l l h x cbr/self illegal 11 llllopcodemrs illegal 11 write hxxxx dsel nop recoveringlhhhx nop nop with auto l h l h ba,ca,a10 read/readap illegal 2,7,10 precharge l h l l ba,ca,a10 writ/writeap illegal 2,10 l l h h ba,ra act illegal 2,10 l l h l ba,a10 pre/pall illegal 2,11 l l l h x cbr/self illegal 11 llllop codemrs illegal 11 refreshinghxxxx dsel nop lhhhx nop nop l h l x x read/ readap illegal 11 l l h x x act/pre/pall illegal 11 l l l x x cbr/self/mrs illegal 11 mode register hxxxx dsel nop-enter idle after tmrd accessinglhhhx nop nop-enter idle after tmrd l h l x x read/write/ readap/ writeap illegal 11 l l x x x act/pre/pall/ cbr/self/mrs illegal 11 notes: key: h: high level, l: low level, x: dont care, v: valid data input, ba: bank address, ap: auto precharge, ca: column address, ra: row address. *all entries assume that cke was active (high level) during the preceding clock cycle.
82443MX pciset 68 1. if both banks are idle and cke is inactive (low level), then in power down mode. 2. illegal to bank in specified states. function may be legal in the bank indicated by bank address (ba), depending on the state of that bank. 3. if both banks are idle and cke is inactive (low level), then in self refresh mode. 4. illegal if trcd is not satisfied. 5. illegal if tras is not satisfied. 6. must satisfy burst interrupt condition. 7. must satisfy bus contention, bus turn around, and/or write recovery requirements. 8. must mask preceding data that does not satisfy tdpl. 9. illegal if trrd is not satisfied. 10. illegal for a single bank, but legal for other banks in multi-bank devices. 11. illegal for all banks. 7.2.4 dram address translation and decoding the 440mx address decoders translate the address received on the host bus or pci bus to an effective memory address. translation supports 16- and 64-mbit dram devices with 2 kb, 4 kb and 8 kb page sizes. page size varies per row depending on how many column address lines are used for a given row. rows containing sdrams with 8 column lines have a 2 kb page size. those with 9 column lines have a 4 kb page size and those with 10 column address lines have an 8 kb page size. the multiplexed row/column address to the dram memory array is provided by the ma[13,12#,11#,10,(9:0)#] signals. the ma[13,12#,11#,10,(9:0)#] bits are derived from the host address bus as defined by table 45. row and column address muxing on the ma[13,12#,11#,10,(9:0)#] lines is determined on a row-by-row basis allowing for three possible page sizes. sdrams have 8, 9 or 10 column lines allowing for 2 kb, 4 kb or 8 kb page sizes. the page size is determined primarily by the row size. when implemented with 2mx32 devices, four banks are supported for that row. that is, up to four pages may be opened within that row. since the 64- mb 2mx32 devices have only eight column address lines, rows using these devices have only a 2 kb page size while those implemented with the 16-mb 2mx8 have nine column address lines yielding a 4 kb page size. the 16-bit page size register is used to distinguish between page sizes for a 32-mb sdram row. it contains a bit per row to specify the page size for that row. when a bit is set to 1, the 440mx uses the larger of the two possible page sizes. table 45 shows the address muxing requirements for each of the supported row sizes. row size is internally computed using the values programmed in the drb registers. page size is determined by the row size and the page size register. note that the column address for the 32 m, 64 m and 128 m row sizes has p for ma10. p is sent out on ma10. either two or four pages can be open at any time within any row. if a row contains sdrams based on 16-mb technology (i.e., 12x8/9/10 devices), then two pages can be open at a time within that row. if a row contains sdrams based on 64-mb technology, (i.e., 14x8/9/10 devices) then four pages can be open at a time within that row.
82443MX pciset 69 the sdram components used for the options shown in table 45 have the following configurations: option sdram component type 1 (8 mb) 1m x 16 2 (16 mb) 2m x 8 3 (32 mb) 4m x 16 4 (64 mb) 8m x 8 5 (128 mb) 16m x 8 note: while other options are available, e.g., 8mx16 configuration for the 64 mb option or 2mx32 configuration for the 16 mb option, intel has not tested them. table 45. ma muxing vs. dram address split max. address row size split row/ col sdram a11 ba1 ba0 a10/ ap a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 option 1 1 12x8*row 1112 14132221201918171615 8 mb col 11ap 109876543 option 2 2 12x9*row 1223 14132221201918171615 16 mb col 12ap 11109876543 13x8*row 121123 14132221201918171615 col 1211ap 109876543 option 3 3 12x10*row 1323 14242221201918171615 32 mb col 13ap1211109876543 14x8*row 13 121123 14242221201918171615 col 1211ap 109876543 option 4,5 4,5 14x9*row 25 131223 14242221201918171615 64/128 mb col 1312ap 11109876543 note: muxing scheme h C three page sizes, new jedec dimm pinout. 7.2.5 sdramc register programming table 46 summarizes the programmable sdram timing parameters.
82443MX pciset 70 table 46. programmable sdram timing parameters parameter sdramc bit values (sclks) cas# latency cl 2,3 ras#-to-cas# delay srcd 2,3 ras# precharge srp 2,3 leadoff cs# assertion lct 3,4 the sdram timing parameters are controlled via the sdramc register. to support different device speed grades at 66 mhz, cas# latency, ras#-to-cas# delay and ras# precharge are all programmable as either two or three sclks. to provide flexibility, each parameter is controlled by a separate register bit; i.e., any combination of cas# latency, ras#-to-cas# delay and ras# precharge can be supported. one additional bit, the leadoff timing bit, controls cs# assertion when the command lines (sras#, scas# and we#) are considered valid on the interface, and hence when cs# can be asserted for cpu read leadoff cycles. in the fastest timing mode, cs# can be asserted in clock three. this enables a seven-clock page hit performance with cas# latency, two devices and one clock md-to-hd delay. this field controls when the first assertion of cs# occurs for cpu-initiated read cycles. the assertion may be for a read, row activate or precharge command. the ma lines along with the command lines (sras#, scas# and we#) are driven in clock two, however the clock-to-output delay timing is slower than in the other modes. use of this mode may require a lightly loaded sdram interface. 7.2.6 sdram paging policy 7.2.6.1 overview open page arbitration (opa) is a paging policy that leaves pages open when handing off dram ownership among masters, and places no restrictions on the number of rows which may have open pages at any given time. opa features include:  pipelined arbitration allows row/bank/page operations for the next cycle to occur during a current dram access.  maintains two or four open banks, in up to eight rows at a time. 7.2.6.2 open page arbitration policies at any given time, pages may be open in any of the eight rows of sdram memory. for each row, pages can be open simultaneously in each bank, i.e., two banks/row for 16-mbit sdram and (typically) four banks/row for 64-mbit sdram. open page arbitration is always enabled. 7.2.6.3 selective auto precharge policy the selective auto precharge (sap) policy causes the 443bx dram controller to use auto precharge when issuing commands on behalf of certain cycles.
82443MX pciset 71 7.2.7 dram power throttling 7.2.7.1 overview the 440mx provides a mechanism to control the rate of write and read cycles to dram. this mechanism, known as power throttling, includes two independent hardware functions, one for write throttling and the other for read throttling. write throttling is provided to avoid over-heating when the system generates write traffic to dram in a higher rate than specified for a sustained period of time. a high write rate can fail the system and cause permanent damage to the 440mx. the read throttling is provided to avoid over-heating the sdram components when the system generates read traffic to dram in a higher rate than specified, for a sustained period of time. such high read rates can fail the system. 7.2.7.2 conceptual description of power throttling since read and write throttling operate similarly, the power throttling sequences described in sections 7.2.7.2.1 and 7.2.7.2.2 apply to both functions. 7.2.7.2.1 during monitoring regime  a global sampling window is used as a period of monitoring the dram traffic.  during the sampling window, the number of transferred qword writes (for write throttling) and reads (for read throttling) are counted.  at the end of the sampling window, the accumulated qword count is compared to a global qw threshold. if the count is higher than the threshold, then a throttling regime is entered; otherwise, the sequence repeats itself without performing throttling.  the threshold is selected based on the systems bandwidth threshold that guarantees that the 440mx temperature remains under the specified value. for example, if the sampling window is 1 second, the maximum sustained bandwidth is 500 mb/s than the desired threshold is 500/8 = 62.5m qw.  the choice of sampling window is made based on the temperature gradient, resulted by a change of bandwidth from some steady state to the maximum bandwidth. the sampling window of choice is expected to be a fraction of and up to one second.  note that during the monitoring regime, no throttling occurs. only the transfers are counted. 7.2.7.2.2 during throttling regime  a throttling time is selected for the throttling regime duration. the throttling time can be set to an integer of 1 to 63 times the global sampling window.  the throttling time is selected in a manner that optimizes the relationship between the throttling factor and the throttling duration. to achieve a given average bandwidth that guarantees the desired component temperature, throttling can be deeper for a shorter time or not as deep for a longer time. for example, assuming a maximum bandwidth of 800 mb/s and a desired sustained bandwidth of 500 mb/s, if the sampling period is set to one second, then the 500 mb/s can be achieved by throttling for one second down to 200 mb/s, or by throttling for two seconds at 350 mb/s.  the throttling time is further divided into sub-periods called throttle monitoring windows. while a typical throttling time is one or more seconds, each throttle monitoring window period is typically 10 microseconds.
82443MX pciset 72  for each throttle monitoring window, the throttling function allocates a budget of throttle qw max that can be performed to dram. within a throttle monitoring window, once the budget of qw transfers (reads for read throttling, writes for write....) have completed, all further cycles (associated with the specific throttling function) are blocked. in the end of the throttle monitoring window period, all transfers are re-enabled and the new budget of transfers is allocated.  the throttle qw max budget is selected in accordance with the throttle monitoring window and based on the bandwidth desired while throttling. for example, if the throttle window is selected to be 10 microseconds and the desired throttle bandwidth is 350 mb/s then the selected throttle qw max is ~437 qwords.  the throttling process repeats itself in each throttle monitoring window. if the selected throttling time is two seconds and the throttle monitoring window is 10 microseconds, then the process is performed 200,000 times. at the end of the throttling regime, the 440mx returns to the monitoring regime and the sequence described in sections 7.2.7.2.1 and 7.2.7.2.2 repeats itself. 7.2.7.2.3 read and write throttling regimes in a write throttling regime, once mask conditions are met, the 440mx dram arbiter blo cks all writes. it attempts not to block reads by granting read requests to dram that can be performed independently of the blocked writes. for example, read requests that do not match posted writes addresses can be performed. however, if a read address matches the address of a posted write, both the read and write are blocked. in a read throttling regime, once mask conditions are met, the 440mx dram arbiter blo cks all cycles to dram, reads and writes. the 440mx guarantees that a minimum required refresh rate is maintained through the throttling regime. 7.2.7.2.4 the relation between read and write throttling read and write throttling hardware functions are completely independent and allow all of the following states:  both read and write functions are in the monitoring regime.  read is monitoring while write is throttling.  write is throttling while read is monitoring.  both read and write functions are in the throttling regime, where:  read function is actively masking all cycles.  write function is actively masking writes.  none of the functions is actively masking.  both functions mask and effectively all cycles are blocked. although the hardware is independent for both functions, some system scenarios cannot occur. for example, once the read function transitions into a throttling regime (while the write is in a monitoring regime), the write function remains in its state since all cycles are blocked by the read function. 7.2.7.3 sdram power throttling setting sequence the following sequence must be followed to correctly set the power throttling functions: 1. set the following write throttling fields: gdwsw, gqt, tt, tmw, and tqm. 2. set the following read throttling fields: gdrsw, rgqt, rtt, rtmw, and rtqm.
82443MX pciset 73 3. enable the throttling functions by setting bit 2 of each of the corresponding registers. bits 1:0 of these registers must be 00 at all times. note that the above throttling fields must be set to non-zero values before the functions are enabled. 4. set the tlock bit. once tlock is set to a 1, the throttling registers can be read but cannot be modified. once locked, throttling function attributes can be modified after the next cold reset. 5. as an option, serr# generation may be enabled when throttling conditions are met, if the platform needs to generate an interrupt for this case. serr# generation is not protected by tlock. 7.2.8 sdram performance description the overall sdram performance is controlled by the dram timing register, the pipelining depth used in the 440mx, and the dram speed grade. in addition, exact system performance depends on the total memory supported, external buffering and memory array layout. as frequencies increase, the flight times for dram signals become important and contribute to the performance achieved. 7.2.9 sdram optimizations 7.2.9.1 dual and quad bank support the 440mx supports 16-mb, 64-mbit, and 128-mbit sdram technology. when 16-mb sdrams are used for a particular row of memory, the 440mx uses 12x8/9/10 (row x column) addressing and can keep up to two pages open within that row. when 64-mb technology is used for a particular row of memory, the 440mx uses 14x8/9/10 or 13x8 (in the case of a row containing two 2mx32 sdram devices) addressing and can keep up to four pages open within that row provided the sdrams support four banks. some 64-mb sdrams may be available with only a two-bank architecture. these parts are also supported by the 440mx. note that when a 2mx32 sdram device is used and the device is a two-bank implementation, the addressing for this part is the same as for a 2mx8 (16mb) device, or 12x9. the banks per row bits (bpr) in the paging policy register are used to indicate two versus four-bank sdrams on a row-by-row basis. each bit in the eight-bit bpr field corresponds to one row of memory. when a bit is set to 0, it indicates that the corresponding row has only two banks. when a bit is set to 1, it indicates that the corresponding row has four banks and thus can have up to four pages open at any time. the banks per row information is obtained by the bios via the serial presence detection port on the sdram dimms and then programmed into the bpr field. 7.3 system memory management 7.3.1 smram range overview the 440mx supports the use of main memory as system management ram (smram) enabling the use of system management mode. the 440mx supports two smram options: compatible smram (c_smram) and extended smram (e_smram). smram space provides a memory area that is available for the smi handler's and code and data storage. this memory resource is normally hidden from the system os so that the processor has immediate access to this memory space upon entry to smm. the 440mx provides the following three smram options:  below 1 mbyte option that supports compatible smi handlers.  above 1 mbyte option that allows new smi handlers to execute with write-back cacheable smram.
82443MX pciset 74  optional larger write-back cacheable t_seg area from 128 kb to 1 mb in size above 1 mbyte that is reserved from the highest area in system dram memory. the above 1 mbyte solutions require changes to compatible smram handler code to properly execute above 1 mbyte. 7.3.2 compatible smram (c_smram) compatible smram is the traditional smram feature supported in intel chipsets. when this function is enabled via c_base_seg[2:0]=010 and g_smrame=1 of the smramc register, the 440mx reserves 000a0000h through 000bffffh (a and b segments) of the main memory for use as non-cacheable smram. cpu accesses to segments a and b while not in smm are always forwarded to the pci bus. cpu accesses to segments a and b while in smm are forwarded to either the dram or the pci bus depending on the value of bits[6:0] of the smramc register. pci masters cannot access the smram area of the main memory. when a pci master tries to access the smram space, the 440mx does not respond to the pci cycle (i.e., devsel# is not asserted). the a and b segments are non-cacheable memory space. in this configuration, the smram space is aliased with the graphics frame buffer memory. the 440mx separates smram space from system space by directing the cycle to either the dram memory or to the pci bus. for example, when the processor is executing in one of its normal operating modes, then any access to the a or b segments is directed to the pci bus, where it is then claimed by the graphics controller. however, when the processor generates a cycle to the a or b segments while in smm, then this access is directed to the a or b segment of dram (and is not sent to the pci bus). when the system is initialized, setting the d_open configuration bit is used to force accesses to the designated smram memory while the processor is operating in one of its normal operating modes. during this time the smi handler is copied to the smram area. the smi handler can set the cls bit to enable data accesses to aliased memory space, while code fetches access the smram space. 7.3.3 extended smram (e_smram) this feature extends the smram space up to 1 mbyte and provides write-back cacheability. the tseg size is 128 kbytes, 256 kbytes, 512 kbytes or 1 mbyte, as defined by tseg_sz[1:0] of the smramc register. when tseg is enabled, then the tseg block of memory is disabled from the top of memory and the system bios should report a main memory size (memory size - tseg) to the os. the extended smram space has a fixed location in the cpu address space between 256 mb and 512 mb. table 47 shows the two areas of memory available for smram when extended smram is enabled. table 47. available memory for smram when extended smram enabled physical address dram address 100a0000h to 100fffffh 000a0000h to 000fffffh (high mem) 10000000h plus tom minus tseg_sz to 10000000h plus tom tom minus tseg_sz to tom (tseg) table 48 shows the available dram memory of the extended smram option.
82443MX pciset 75 table 48. extended smram dram memory regions dram area size/availability a, b segments 64 kbytes always available if enabled (i.e., g_smrame = 1 and h_smrame=1) tseg 128k, 256k, 512k or 1 mb available if enabled (i.e., tseg_en=1 and g_smrame = 1) as with the compatible smram solution, the 440mx does not claim any bus master access to the extended smram memory ranges defined earlier. the d-opn, dlck and d_cls bits provide the same functions as in compatible smram. the cpu can access these memory ranges by one of the following mechanisms:  the processor can access smram while in the smm mode. a processor access to smram while not in smm and while the d_opn bit is reset, is forwarded to the pci bus and a status bit is set in the smramc register.  the processor can access smram while the d_opn bit is set. figure 7 illustrates how smram is mapped for various smram ranges. table 49 summarizes the operation of smram space cycles targeting the smi space addresses. the compatible smram region at a is always available. the h_srmame bit controls accesses to the high smram range h. the tseg_en bit independently controls the extended smram range t. smram regions are decoded as follows: a = 0a0000 to 0bffffh h = 100a0000h to 100fffffh t = (256m + tom-segment) to (256m + tom) table 50 defines the decode control for all code fetches and data fetches to smram ranges (as defined by table 49). the g_smram bit provides a global disable for all smram memory. the d_open bit allows software to write to the smram ranges without being in smm. bios software can use this bit to initialize smm code at powerup. the d_lck bit limits the smram range access to only smm mode accesses. the d_cls bit causes smm data accesses to be forwarded to pci. the smm software can use this bit to write to video memory while running code out of dram.
82443MX pciset 76 257 mb 4 gb tom-tseg_sz t-se g ment re g ion ( cacheable ) 256+tom-tseg_sz 256+1 mb 256 + tom 512 mb cacheable re g ion cacheable re g ion cacheable re g ion top of memor y ( tom ) top of dram ( tod ) 128 mb 1 mb 640 kb 257 mb le g ac y smram memor y re g ion low-memor y hi g h smram memor y cacheable re g ion ( remappin g from below 1 mb ) hi g h-memor y figure 7. smram mapping
82443MX pciset 77 table 49. smram range decode smram decode h_smrame tseg_en a range h range t range disable x x disable disable disable enable 0 0 enable disable disable enable 0 1 enable disable enable enable 1 0 enable enable disable enable 1 1 enable enable enable table 50. smram decode control g_smrame d_lck d_cls d_open smm mode smm code fetch smm data fetch 0 x x x x disable disable 1 0 x 0 0 disable disable 1 0 0 0 1 enable enable 1 0 0 1 x enable enable 1 0 1 0 1 enable disable 1 0 1 1 x invalid invalid 1 1 x x 0 disable disable 1 1 0 x 1 enable enable 1 1 1 x 1 enable disable 7.4 ac97 audio and modem controller 7.4.1 ac97 audio controller this section is based on the ac97 rev 2.0 specification (draft rev. 0.96). ac'97 includes the following audio features:  independent (fdx) channels for stereo pcm in, stereo pcm out, and mono mic in  supports 16-bit samples for stereo pcm out  supports multiple sample rate ac'97 2.0 codecs (48 khz and below)  supports dual codec implementations for audio in mobile  supports read/write access to all primary and secondary ac'97 registers
82443MX pciset 78 the 440mx does not support the following ac97 rev 2.0 specification features:  support for additional 4 channels of pcm (center, l surround, r surround, lfe)  support for optional double rate sampling (n+1 sample for pcm l, r & c)  support for 18- and 20-bit sample lengths 7.4.2 ac97 modem controller the 440mx includes the following ac'97 softmodem features:  independent (fdx) channels for mono line in and out  supports 16-bit samples  supports multiple sample rate ac'97 codecs (48 khz and below)  supports ac'97 dual codec implementations for ac'97 audio and modem afe  supports read/write access to all primary and secondary ac'97 registers  supports low latency access to 16 gpio and wake-up event status bits note:  the 440mx does not support line 2 dac/adc for the modem which is defined by the ac97 specification.  the 440mx does not support the handset channels (in and out).  the 440mx supports only 16-bit modem samples. 7.4.3 ac97 overview figure 8 illustrates how the ac97 controller communicates with its companion ac97/amc97 codec via a digital serial link, ac-link. all digital audio streams, modem line codec streams, and command/status information are communicated over this point-to-point serial interconnect. figure 9 shows the audio connections of a 440mx-based ac97 audio system. table 51 describes the signals that connect the ac97 controller with the ac97/amc97 codec. the ac'97 modem controller is a separate pci function. however, the ac'97 modem controller is implemented in the same logical unit as the ac'97 audio functions.
82443MX pciset 79 primar y codec ac_sync ac_bit_clk ac_sdata_out ac'97 / ac'97 2.0 / amc'97 di g ital ac'97 controller ac_rst# ac_data_in_0 secondar y codec ac_data_in_1 ac'97 2.0 / mc'97 / amc'97 figure 8. ac97 controller connection to its companion codec audio in ( record ) audio out ( pla y back ) modem mic. pc figure 9. 440mx-based ac97 audio system table 51. ac97 audio pin description signal type description ac_bit_clk i 12.288 mhz serial data clock ac_sdata_in_1 i serial tdm ac97 input data ac_sdata_in_0 i serial tdm ac97 input data ac_rst# o ac97 master hw reset ac_sdata_out o serial tdm ac97 output data
82443MX pciset 80 ac_sync o 48 khz fixed rate sample sync 7.4.4 system initialization the ac'97 circuitry is reset on power up by combining the pcirst# signal with the ac'97 ac_rst# signal. the ac_rst# signal remains asserted (low) until the driver writes the cold reset bit in the global control register to 1 (either the audio or the modem driver can do this, because setting this bit in any one register will suffice since they both reflect the same register). during operation, the system can be reset by clearing the ac'97 ac_rst# bit in the global control/status register (nabmbar + 60h). after reset, a read to mixer register 00h indicates what type of hardware resides in the codec. if the codec is not present, i.e., ac'97 is not supported, codec ready is never seen by the controller. 7.4.5 clocking the ac97 codec derives its clock internally from an externally attached 24.576 mhz crystal 1 , and drives a buffered and divided down (1/2) clock to its digital companion controller over ac-link under the signal name bit_clk. clock jitter at the dacs and adcs is a fundamental impediment to high quality output, and the internally generated clock provides ac97 with a clean clock that is independent of the physical proximity of ac97s companion digital controller (henceforth referred to as the ac97 controller). the secondary codec is clocked by the bit_clk supplied by the primary codec. the beginning of all audio sample packets, or audio frames, transferred over ac-link is synchronized to the rising edge of the sync signal. sync is driven by the ac97 controller. the ac97 controller takes bit_clk as an input and generates sync by dividing bit_clk by 256 and applying some conditioning to tailor its duty cycle. this yields a 48 khz sync signal whose period defines an audio frame. data is transitioned on ac-link on every rising edge of bit_clk, and subsequently sampled on the receiving side of ac-link on each immediately following falling edge of bit_clk. 7.4.6 digital interface 7.4.6.1 multi-point aclink the multi-point aclink method allows up to two codecs on the link. by definition there is a primary and a secondary codec. the two devices have completely orthogonal register sets, i.e., they do not share registers and each is individually accessible. both devices share sdata_out from the controller, but each has its own sdata_in pin back to the controller. this prevents contention of the two devices on one input. it also keeps any unnecessary complexity from the codecs. 7.4.6.1.1 primary codec the primary device is completely backwards compatible with existing ac97 solutions. it generates the master bit_clk for both the controller and the secondary codec. its registers are located in the same place as defined in ac97. the primary codec can only be an ac97, ac97 rev 2.0 or an amc97. 1 a 24.576 mhz crystal is recommended, but an external oscillator may also be input to ac 97 xtal_in.
82443MX pciset 81 7.4.6.1.2 secondary codec the secondary device can only be an ac97 2.0, mc97, amc97 or completely compatible to one of those devices. the secondary devices bit_clk pin must be configured as an input. inside, the bit_clk must be multiplied by two so that the internal rate is 24.576 mhz. 7.4.6.2 ac-link digital serial interface protocol each ac97 codec incorporates a five-pin digital serial interface that links it to the ac97 controller. ac-link is a bi-directional, fixed rate, serial pcm digital stream (see figure 10). it handles multiple input and output audio streams, as well as control register accesses employing a time division multiplexed (tdm) scheme. the ac-link architecture divides each audio frame into 12 outgoing and 12 incoming data streams, each with 20-bit sample resolution. with a minimum required dac and adc resolution of 16 bits, ac97 can also be implemented with 18- or 20-bit dac/adc resolution, given the headroom that the ac-link architecture provides. table 52 lists the data streams supported by the 440mx. table 52. supported data streams channel slots comments pcm playback 2 output slots 2-channel composite pcm output stream pcm record data 2 input slots 2-channel composite pcm input stream control 2 output slots control register write port status 2 input slots control register read port modem line codec output 1 output slot modem line codec dac output stream modem line codec input 1 input slot modem line codec adc input stream dedicated microphone input 1 input slot dedicated microphone input stream to support stereo aec, and/or other voice applications i/o control 1 output slot one slot dedicated to gpios on the modem codec i/o status 1 input slot one slot dedicated to status from gpios in the modem codec, with data returned on every frame the ac97 controller signals the synchronization of all ac-link data transactions. the primary codec drives the serial bit clock onto ac-link, which the ac97 controller then qualifies with a synchronization signal to construct audio frames. sync, fixed at 48 khz, is derived by dividing down the serial bit clock (bit_clk). bit_clk, fixed at 12.288 mhz, provides the necessary clocking granularity to support 12, 20-bit outgoing and incoming time slots. ac- link serial data is transitioned on each rising edge of bit_clk. the receiver of ac-link data, ac97 for outgoing data and ac97 controller for incoming data, samples each serial bit on the falling edges of bit_clk.
82443MX pciset 82 the ac-link protocol provides for a special 16-bit 2 time slot (slot 0) wherein each bit conveys a valid tag for its corresponding time slot within the current audio frame. a 1 in a given bit position of slot 0 indicates that the corresponding time slot within the current audio frame has been assigned to a data stream, and contains valid data. if a slot is tagged invalid, it is the responsibility of the source of the data, (ac97 for the input stream and ac97 controller for the output stream), to stuff all bit positions with 0s during that slots active time. sync remains high for a total duration of 16 bit_clks at the beginning of each audio frame. the portion of the audio frame where sync is high is defined as the tag phase. the remainder of the audio frame where sync is low is defined as the data phase. sync outgoing streams incoming streams tag tag cmd adr cmd data pcm left pcm right mdm cdc rsrvd rsrvd rsrvd rsrvd i/o control status adr status data pcm left pcm right mic rsrvd rsrvd rsrvd rsrvd rsrvd i/o status slot # 012345 mdm cdc 6789101112 data phase ta g phase rsrvd rsrvd figure 10. ac97 standard bi-directional audio frame 7.5 pci interface 7.5.1 pci interface overview the 440mx pci bus interface is compliant with the pci local bus specification , revision 2.2. the implementation is optimized for high-performance data streaming when the 440mx is acting as either the target or the initiator on the pci bus. the 440mx integrates the traditional north and south bridges/clusters with additional features into a single chip with the point of integration being the pci bus (see figure 11). this bus is routed out to the chip interface and forms the pci interface to the external pci devices. 2 13 bits defined, with three reserved trailing bit positions.
82443MX pciset 83 north brid g e / cluster south brid g e / cluster pci bus 440mx figure 11. 440mx pci bus topology 7.5.2 north bridge/cluster functionality 7.5.2.1 north bridge/cluster as a pci target table 53 summarizes the pci transactions supported by the north bridge/cluster when acting as a target. table 53. pci commands supported by the north bridge/cluster when acting as a pci target pci command c/be[3:0]# 440mx north bridge/cluster encoding cycle destination response as pci target interrupt acknowledge 0000 n/a no response special cycle 0001 n/a no response i/o read 0010 n/a no response i/o write 0011 n/a no response reserved 0100 n/a no response reserved 0101 n/a no response memory read 0110 main memory short read memory write 0111 main memory posts data reserved 1000 n/a no response reserved 1001 n/a no response
82443MX pciset 84 pci command c/be[3:0]# 440mx north bridge/cluster encoding cycle destination response as pci target configuration read 1010 n/a no response configuration write 1011 n/a no response memory read multiple 1100 main memory long read dual address cycle 1101 n/a no response memory read line 1110 main memory short read memory write and invalidate 1111 main memory posts data note: n/a refers to a function that is not applicable. as a target of a pci cycle, the north bridge/cluster function only supports the following transactions:  memory read and memory read line . these commands are supported as short reads by the north bridge/cluster. the north bridge/cluster issues a single snoop on the host bus for a short read and releases the cpu bus for other traffic. the pci cycle is disconnected at the cache line boundary if it bursts across the line boundary. using these commands to burst more than a single cache line will result in a performance loss for a pci device during concurrent cpu traffic. the north bridge/cluster handles memory read and memory read line from the south bridge/cluster as a short read.  memory read multiple . this is supported as a long read by the north bridge/cluster. the north bridge/cluster issues a pair of snoops (a snoop followed by a snoop-ahead) on the host bus for a long read and releases the cpu bus for other traffic. if the pci burst cycle is still in progress, the north bridge/cluster reacquires the host bus for the next pair of snoop-aheads. this provides data streaming to the pci devices while allowing the cpu-to-dram access. this specifically reduces wasted host clock cycles where the host bus is running much faster than the pci bus. the south bridge/cluster does not use memory read multiple and is disconnected at the cache line boundary. the north bridge/cluster does not internally request more than two lines to avoid the necessary snoops and data discards.  memory write and memory write and invalidate . these commands are aliased and processed identically. the north bridge/cluster supports data streaming for pci-to-dram writes based on its ability to buffer up to 64 bytes (16 qwords) of data before a snoop cycle must be completed on the host bus. the north bridge/cluster is typically able to support longer write bursts, with the maximum length dependent upon concurrent host bus traffic during pci-dram write data streaming.  other commands . other commands such as i/o r/w and configuration r/w are not supported by the north bridge/cluster as a target and will result in a master abort.  exclusive access . the north bridge/cluster as a target does not support pci locked cycles.  fast back-to-back transactions . the north bridge/cluster as a target does not support fast back-to- back cycles from a pci initiator. 7.5.2.2 north bridge/cluster as a pci initiator as a pci initiator, the north bridge/cluster is responsible for translating host cycles to pci cycles. the north bridge/cluster is a non-caching agent on the pci bus since cacheability is not supported for pci. table 54 lists all of the host cycles that must be translated.
82443MX pciset 85 table 54. pci commands supported by north bridge/cluster when acting as a pci initiator 440mx north bridge/cluster source bus command other encoded information corresponding pci command c/be[3:0]# encoding deferred reply dont care none n/a interrupt acknowledge length  8 bytes interrupt acknowledge 0000 (be[3:0]# = 1110) special cycle shutdown special cycle 0001 (ad[15:0] = 0000h) halt special cycle 0001 (ad[15:0] = 0001h) stop grant special cycle 0001 (ad[15:0] = 0002h, ad[31:16] = 0012h) all other combinations none n/a branch trace message none none n/a i/o read length  8 bytes up to 4 byte enables asserted i/o read 0010 i/o write length  8 bytes up to 4 byte enables asserted i/o write 0011 length < 8 bytes without all bes asserted memory read 0110 memory read (code or data) or length = 8 bytes with all bes asserted memory read 1110 memory read invalidate length = 16 bytes none n/a length = 32 bytes code only memory read 1110 memory write length < 8 bytes without all bes asserted memory write 0111 length = 16 bytes none n/a length = 32 bytes memory write 0111 locked access all combinations locked pci access as applicable reserved encodings all combinations none n/a ea memory access address 4gb none n/a note: n/a refers to a function that is not applicable; not supported refers to a function that is available but specifically not implemented on the north bridge/cluster.
82443MX pciset 86 as an initiator of pci cycles, the north bridge/cluster only supports the following transactions:  memory read and memory read line. for cpu-to-pci reads, the north bridge/cluster only uses memory read.  memory read multiple . the north bridge/cluster as a pci initiator does not support this command.  memory write and memory write and invalidate . the north bridge/cluster initiates pci cycles on behalf of the cpu. the north bridge/cluster does not issue memory write and invalidate as an initiator. the north bridge/cluster does not support write merging or write collapsing. the north bridge/cluster combines cpu-to-pci writes (dword or qword) to provide bursting on the pci bus.  i/o read and write . all i/o reads and writes are forwarded to the pci bus.  exclusive access . exclusive access is established by asserting the lock# signal per the pci specification. the north bridge/cluster issues a locked cycle on the pci bus on behalf of the cpu. the north bridge/cluster retries the initial read of the locked sequence on the host bus to complete snoops for any pending cycles in the pci in queues. the north bridge/cluster advances the locked cycle to the pci bus. once the data is received at the host interface, the north bridge/cluster waits for the cpu to retry the locked cycle. a locked path from cpuCto-pci is established as soon as the host retries the locked access. if the locked access is retried on the pci bus, the north bridge/cluster continues to retry the cycle until it is established.  configuration read and write. configuration accesses to north bridge/cluster registers are consumed internally without reflection on the pci bus. other configuration cycles are forwarded normally. the north bridge/cluster does not accept configuration cycles as a target from the pci bus.  fast back-to-back transactions . the north bridge/cluster as an initiator does not perform fast back-to- back cycles. 7.5.2.3 delayed transactions the 440mx supports delayed transactions for pci-to-dram read cycles only. delayed transaction refers to a retried read transaction termination by the north bridge/cluster as a target, in which no data is transferred but the transaction is enqueued and processed. the 440mx issues a delayed transaction for a read cycle that would require more than 32 pci clo cks to complete for the first data phase, or if the pci out buffer has a cycle queued towards the pci bus. both the delayed transaction enable (dte, register <0xf4h>) and the delayed transaction timer (dtt, register <0xf6h>) are programmable as either enabled or disabled in the north bridge/cluster. if either one is disabled, the pci-to-dram read transaction is held in wait states until the transaction completes. a connected pci-to-dram read can be terminated with a delayed transaction prior to the expiry of the dtt in the following scenario: if the cpu enqueues a pci write transaction outside the snoop window, before the current read data is available in the pci out data buffers for the connected read. the cpu-to-pci transaction has effectively sneaked ahead of the pci-to-dram read in this case. note: this pci transaction is handled as a delayed transaction and when the data is available, it is stored in the delayed transaction buffer. any subsequent cpu-to-pci write transactions are guaranteed to follow the delayed transaction. this ensures that livelock does not occur, in which cpu-to-pci write transactions always precede the pci-to-dram read, resulting in starvation. the 440mx implements a discard timer (dt) that waits for 1024 pci clo cks within which the pci initiator must return with the same access (address must be same, c/bes are dont care) that was terminated with a delayed transaction. if the access is not completed within 1024 pci clo cks, the data retrieved from dram is discarded. the 440mx also discards the data if a pci agents write hits within two consecutive cache lines
82443MX pciset 87 after the starting address of the delayed transaction. a locked cpu cycle queued while data is being acquired for the pending delayed transaction also results in data discard. 7.5.3 south bridge/cluster functionality the pci logic in the south bridge/cluster serves as the pci interface for cycles to and from dma, rtc, interrupt controllers, smbus, gpios, power management logic, usb, ide and x-bus. 7.5.3.1 south bridge/cluster as a pci target the south bridge/cluster accepts cycles on the pci bus on behalf of dma, rtc, interrupt controllers, smbus, gpios, power management, usb, ide, x-bus, and all south bridge/cluster configuration registers. note, however, that the north bridge/cluster is the initiator in many of the cycles directed to the south bridge/cluster. the south bridge/cluster does positive/subtractive decoding depending on the mode selected. table 55 lists all of the pci cycles that the south bridge/cluster can accept as a target. table 55. pci commands supported by the south bridge/cluster when acting as a pci target pci command c/be[3:0]# encoding notes interrupt acknowledge 0000 interrupt controller can receive these cycles special cycle 0001 halt, shutdown, stop grant cycles i/o read/ i/o write 0010/ 0011 many of the functions have i/o ranges that can be disabled and/or relocated. reserved 0100 n/a reserved 0101 n/a memory read/ memory write 0110/ 0111 usb, x-bus can receive these cycles reserved 1000 n/a reserved 1001 n/a confi g uration read/ configuration write 1010/ 1011 south bridge/cluster decodes type 0 configuration cycles to bus #0, device #7 for the south bridge/cluster internal pci devices. memory read multiple 1100 aliased to memory read dual address cycle 1101 n/a memory read line 1110 aliased to memory read
82443MX pciset 88 pci command c/be[3:0]# encoding notes memory write and invalidate 1111 aliased to memory write note: n/a refers to a function that is not applicable. 7.5.3.2 south bridge/cluster as a pci initiator the south bridge/cluster initiates cycles on the pci bus on behalf of ide, dma, usb, and x-bus when granted by the arbiter. table 56 shows that, as an initiator on the pci bus, the south bridge/cluster can only generate memory and i/o read/write cycles. table 56. pci commands supported by the south bridge/cluster when acting as a pci initiator pci command c/be[3:0]# encoding notes interrupt acknowledge 0000 n/a special cycle 0001 n/a i/o read/ i/o write 0010/ 0011 supported reserved 0100 n/a reserved 0101 n/a memory read/ memory write 0110/ 0111 supported reserved 1000 n/a reserved 1001 n/a configuration read 1010 n/a configuration write 1011 n/a memory read multiple 1100 n/a dual address cycle 1101 n/a memory read line 1110 n/a memory write and invalidate 1111 n/a note: n/a refers to a function that is not applicable.
82443MX pciset 89 7.6 dma controller 7.6.1 register description the 440mx contains dma circuitry that incorporates the functionality of two 82c37 dma controllers (dma-1 and dma-2). the dma registers control the operation of the dma controllers and are all accessible from the host cpu via the pci bus interface. 7.6.2 functional description the dma circuitry incorporates the functionality of two 82c37 dma controllers with seven independently programmable channels (channels 0-3 and channels 5-7). dma channel 4 is used to cascade the two controllers and defaults to cascade mode in the dma channel mode (dcm) register. in addition to accepting requests from dma slaves, the dma controller also responds to requests that are initiated by software. software may initiate a dma service request by setting any bit in the dma channel request register to a 1. the dma controller for channels 0-3 is referred to as "dma-1" and the controller for channels 4-7 is referred to as "dma-2." each dma channel is hardwired to the compatible settings for dma device size: channels [3:0] are hardwired to 8-bit, count-by-bytes transfers, and channels [7:5] are hardwired to 16-bit, count-by-words (address shifted) transfers. the 440mx provides the timing control and data size translation necessary for the dma transfer between the memory (dram) and the x-bus i/o. isa-compatible timing is supported. the 440mx provides 24-bit addressing in compliance with the isa-compatible specification. each channel includes a 16-bit isa-compatible current register which holds the 16 least-significant bits of the 24-bit address, an isa-compatible page register that contains the eight next most significant bits of address. the dma controller also features an auto-initialization following a dma termination. at any time, the 440mx controller is either in master mode or slave mode. in master mode, the dma controller services a dma slave request for dma cycles. isa masters are not supported. in slave mode, the 440mx monitors both the x-bus and the pci bus, decoding and responding to i/o read and write commands that address its registers.
82443MX pciset 90 dma-1 dma-2 channel 0 channel 1 channel 2 channel 3 channel 5 channel 6 channel 7 channel 4 sio-45.drw figure 12. internal dma controller note that any dma device (i/o device) always resides on the x-bus, and that the referenced memory is located in system memory. when the 440mx is running a compatible dma cycle, it drives the memr# and memw# strobes if the address is less than 16 mbytes (000000h - ffffffh). if the address is greater than 16 mbytes (1000000h - 7ffffffh), the memr# or memw# strobe are not generated in order to avoid aliasing problems. also, during dma memory read cycles to the pci bus, the 440mx returns all 1's to the x-bus if the pci cycle is either target aborted or master aborted. 7.6.2.1 dma transfer modes dma channels can be programmed for any of three transfer modes: single, block and demand. each of the active transfer modes can perform three different types of transfers (read, write, or verify). note that memory- to-memory transfers are not supported. 7.6.2.1.1 single transfer mode in single transfer mode, the dma is programmed to make one transfer only. the byte/word count is decremented and the address decremented or incremented following each transfer. when the byte/word count "rolls over" from zero to ffffh, a terminal count (tc) causes an auto-initialize if the channel has been programmed to do so. to be recognized, dreq must be held active until dack# becomes active. if dreq is held active throughout a single transfer, the bus is released after the single transfer. with dreq asserted high, the dma i/o device re-arbitrates for the bus. upon winning the bus, another single transfer is performed.
82443MX pciset 91 7.6.2.1.2 block transfer mode in block transfer mode, the dma is activated by dreq to continue making transfers during the service until a terminal count (tc), caused by a byte/word count going to ffffh, is encountered. dreq must be held active only until dack# becomes active. if the channel has been programmed for it, an autoinitialization occurs at the end of the service. in this mode, it is possible to lock out other devices for a period of time if the transfer count is programmed to a large number. note that block mode transfers are not supported with type-f dma. 7.6.2.1.3 demand transfer mode in demand transfer mode, the dma channel is programmed to continue making transfers until a tc is encountered, or until the dma i/o device releases dreq. thus, transfers may continue until the i/o device has exhausted its data capacity. after the i/o device catches up, the dma service is re-established when the dma i/o device reasserts the channel's dreq. during the time between services when the system is allowed to operate, the intermediate values of address and byte/word counts are stored in the dma controller current address and current byte/word count registers. a tc can cause an autoinitialize at the end of the service, if the channel has been programmed for it. 7.6.2.1.4 cascade mode cascade mode is not supported. 7.6.2.2 dma transfer types each of the three active transfer modes (single, block, or demand) can perform three different types of transfers: read, write and verify. 7.6.2.2.1 read transfers read transfers move data from the system dram to an x-bus i/o device. the 440mx activates the iow# command and the appropriate dram memory control signals to indicate a memory read. when the cycle involves dram, the pci read transaction is initiated as soon as the dma address is valid. 7.6.2.2.2 write transfers write transfers move data from an i/o device to memory located in system dram. for transfers using compatible timing, the pci transfer is initiated after the data is valid on the x-bus. the dma device (i/o device) is an 8-bit device located on the x-bus. 7.6.2.2.3 verify transfer verify transfers are pseudo transfers. the dma controller generates these addresses as in normal read or write transfers. however, the 440mx does not activate the x-bus i/o control lines. only the dack# lines go active. the 440mx asserts the appropriate dack# signal for nine sysclks. if verify transfers are repeated during block or demand dma requests, each additional pseudo transfer adds eight sysclks. the dack# lines are not toggled for repeated transfers.
82443MX pciset 92 7.6.2.3 dma timings isa-compatible timing is provided for dma slave devices that reside on the x-bus. 7.6.2.3.1 dma buffer for compatible transfers the dma buffer is a 4-byte buffer that is used to reduce the pci utilization resulting from dma transfers by x- bus devices. when the dma buffer contains data read from a pci slave that is destined to be transferred to a dma slave, it is in the "read state." data is discarded when there is a change in x-bus ownership as indicated by any dack# signal going inactive. when the dma buffer contains data from an x-bus dma slave that is to be written to a pci slave, it is in the "write state". the 4-byte buffer is flushed when it becomes full. the buffer is also flushed whenever there is a change in x-bus ownership as indicated by any dack# signal going inactive. a subsequent dma cycle will be delayed until the flush is complete. once the buffer is scheduled to be flushed to pci, any pci master read cycle to the south bridge/cluster, x- bus or ide is retried by the south bridge/cluster (writes must not be retried or a "livelock" condition occurs). reads are retried because pci masters cannot be allowed to observe the state changes in devices connected to the x-bus or in the dma controller itself resulting from the dma transfer until the data from that dma transfer is visible in system memory. 7.6.2.3.2 dreq and dack# latency control the 440mx dma arbiter maintains a minimum dreq-to-dack# latency on all dma channels when programmed in compatible mode. this is to support older devices such as the 8272a. the dreqs are delayed by eight sysclks prior to being seen by the arbiter logic. this delay guarantees a minimum 1  s dreq-to-dack# latency. software requests do not have this minimum request to dack# latency. 7.6.2.4 x-bus / dma arbitration the x-bus arbiter evaluates requests for the x-bus coming from three different sources. pci masters have default ownership of the x-bus, while the dma unit may request access to the x-bus through the 440mx arbiter. the dma unit provides a preliminary layer of arbitration for requests from dma channels. pci master cycles have default priority over the 440mx arbiter. the 440mxs x-bus arbiter uses a simple two- way rotating priority arbitration method. the 440mx arbitrates for x-bus control through the internal pci phold# / phlda# protocol when a dma request is pending. if the 440mx performs a pci transaction as a master on behalf of the dma controller and that transaction is terminated with a retry, the 440mx reissues the transaction without de-asserting the internal phold#. (phold# cannot be de-asserted without creating a deadlock situation.) devices are serviced according to their rotation position, independent of the order in which they assert a bus request. this arbitration normally rotates priority after either agent is granted the bus.
82443MX pciset 93 7.6.2.4.1 channel priority for priority resolution the dma consists of two logical channel groups: dma-1 = channels 0-3, and dma-2 = channels 4-7 (see figure 12 in section 7.6.2). each group may be in either fixed or rotate mode, as determined by the dma command register. the source (dreqx) of the dma request is transparent to the final priority resolution logic. a generic request from the dma is sent to the x-bus arbiter. dma i/o slaves normally assert their dreq line to arbitrate for dma service. however, a software request for dma service can be presented through each channel's dma request register. a software request is subject to the same prioritization as any hardware request. please see section 7.6.2 for request register programming details. 7.6.2.4.1.1 fixed priority the initial fixed priority structure is as follows: high priority.....low priority (0, 1, 2, 3) 5, 6, 7 the fixed priority ordering is 0, 1, 2, 3, 5, 6, and 7. in this scheme, channel 0 has the highest priority, and channel 7 has the lowest priority. channels [3:0] of dma-1 assume the priority position of channel 4 in dma- 2, thus taking priority over channels 5, 6, and 7 (see figure 13). dma system (2-way rotation ) ch0 ch1 ch2 ch3 ch5 ch6 ch7 ibisaarb.drw figure 13. x-bus arbiter with dma in fixed priority (2-way rotation) 7.6.2.4.1.2 rotating priority rotation allows for "fairness" in priority resolution. the priority chain rotates so that the last channel serviced is assigned the lowest priority in the channel group (0-3, 5-7). channels 0-3 rotate as a group of four. they are always placed between channel 5 and channel 7 in the priority list. channels 5-7 rotate as part of a group of four. that is, channels 5-7 form the first three positions in the rotation, while channel group (0-3) comprises the fourth position in the arbitration (see figure 14). table 57 demonstrates rotation priority.
82443MX pciset 94 ibisaarb.drw (4-way rotation) dmax ch5 ch6 ch7 (4-way rotation) ch0 ch1 ch2 ch3 figure 14. x-bus arbiter with dma in rotating priority table 57. rotating priority example programmed mode action priority high...............low group (0-3) is in rotation mode 1) initial setting (0, 1, 2, 3), 5, 6, 7 group (4-7) is in fixed mode. 2) after servicing channel 2 (3, 0, 1, 2), 5, 6, 7 3) after servicing channel 3 (0, 1, 2, 3), 5, 6, 7 group (0-3) is in rotation mode 1) initial setting (0, 1, 2, 3), 5, 6, 7 group (4-7) is in rotation mode 2) after servicing channel 0* 5, 6, 7, (1, 2, 3, 0) 3) after servicing channel 5 6, 7, (1, 2, 3, 0), 5 4) after servicing channel 6 7, (1, 2, 3, 0), 5, 6 5) after servicing channel 7 (1, 2, 3, 0), 5, 6, 7 note: *the first servicing of channel 0 caused double rotation. 7.6.2.4.2 arbitration during non-maskable interrupts if a non-maskable interrupt (nmi) is pending, then the dma controller is bypassed each time it comes up for rotation. this gives the cpu the bus bandwidth it requires to process the interrupt as fast as possible. 7.6.2.5 register functionality dma channel 4 is used to cascade the two dma controllers together and should not be programmed for any mode other than cascade. the dma channel mode register for channel 4 defaults to cascade mode. special attention should also be taken when programming the command and mask registers as related to channel 4.
82443MX pciset 95 7.6.2.5.1 addr ess compatibility mode whenever the dma is operating, addresses do not increment or decrement through the high and low page registers. this is compatible with the 82c37 and page register implementation used in the pc-at. this mode is set after cpurst# is valid. 7.6.2.5.2 summary of dma transfer sizes table 58 lists each of the dma device transfer sizes. the column labeled "current byte/word count register" indicates that the register contents represent either the number of bytes to transfer or the number of 16-bit words to transfer. the column labeled "current address increment/decrement" indicates the number added to or taken from the current address register after each dma transfer cycle. the dma channel mode register determines if the current address register will be incremented or decremented. table 58. dma transfer size dma device date size and word count current byte/word count register current address increment/decrement 8-bit i/o, count by bytes bytes 1 16-bit i/o, count by words (address shifted) words 1 7.6.2.5.3 addr ess shifting when programmed for 16-bit i/o count by words the 440mx maintains compatibility with the dma implementation in the pc-at, which used the 82c37. the dma shifts the addresses for transfers to/from a 16-bit device count-by-words. note that the least significant bit of the low page register is dropped in 16-bit shifted mode. when programming the current address register when the dma channel is in this mode, the current address must be programmed to an even address with the address value shifted right by one bit. table 59 shows the address shifting for 16-bit i/o dma transfers. table 59. address shifting in 16-bit i/o dma transfers output address 8-bit i/o programmed address (ch 0-3) 16-bit i/o programmed address (ch 5-7) (shifted) a0 a0 0 ha[16:1] ha[16:1] ha[15:0] ha[23:17] ha[23:17] ha[23:17] note: the least significant bit of the page register is dropped in 16-bit shifted mode. 7.6.2.5.4 autoinitialize by programming a bit in the dma channel mode register, a channel may be set up as an autoinitialize channel. when a channel undergoes autoinitialization, the original values of the current page, current address and current byte/word count registers are automatically restored from the base page, address, and byte/word count registers of that channel following tc. the base registers are loaded simultaneously
82443MX pciset 96 with the current registers by the microprocessor when the dma channel is programmed and remain unchanged throughout the dma service. the mask bit is not set when the channel is in autoinitialize. following autoinitialize, the channel is ready to perform another dma service, without cpu intervention, as soon as a valid dreq is detected. 7.6.2.6 software commands the three additional special software commands that can be executed by the dma controller are:  clear byte pointer flip- flop  master clear  clear mask register these software commands do not depend on any specific bit pattern on the data bus. 7.6.2.6.1 clear byte pointer flip-flop this command is executed prior to writing or reading new address or word count information to/from the dma controller. this initializes the flip-flop to a known state so that subsequent accesses to register contents by the microprocessor will address upper and lower bytes in the correct sequence. when the host cpu is reading or writing dma registers, two byte-pointer flip-flops are used; one for channels 0-3 and one for channels 4-7. both of these act independently and each is cleared by separate software commands (0ch for channels 0-3, 0d8h for channels 4-7). 7.6.2.6.2 dma master clear this software instruction has the same effect as a hardware reset. the command, status, request, and internal first/last flip-flop registers are cleared and the mask register is set. the dma controller enters the idle cycle. the two independent master clear commands are:  0dh acts on channels 0-3  0dah acts on channels 4-7 7.6.2.6.3 clear mask register this command clears the mask bits of all four channels, enabling them to accept dma requests. i/o port 00eh is used for channels 0-3 and i/o port 0dch is used for channels 4-7. 7.6.2.7 terminal count summary table 60 summarizes the events that occur as a result of a terminal count when running dma in various modes.
82443MX pciset 97 table 60. terminal count summary condition autoinit no yes event word counter expired yes x yes x result status tc set set set set mask set set sw request clr clr clr clr current register load load notes: load = load current from base "" = no change x = don't care clr = clear 7.6.2.8 x-bus refresh cycles the 440mx does not support any memory device on the x-bus, hence it does not support or run any refresh cycles on the x-bus. 7.7 pci dma 7.7.1 overview the 440mx supports two types of pci dma protocols: pc/pci and distributed dma. these protocols are completely distinct and are used for different types of peripherals. 7.7.1.1 pc/pci dma this scheme uses dedicated request and grant signals to permit pci devices to request transfers associated with specific dma channels. upon receiving a request and getting control of the pci bus, the 440mx performs a two-cycle transfer. for example, if data is to be moved from the peripheral to main memory, the 440mx first reads the data from the peripheral and then writes it to main memory. the location in main memory is the same as in the 8237current address registers. the 440mx supports one pc/pci req/gnt pair. request and grant pairs used as expansion (bus master) signals are not supported. request and grant pairs dedicated to a specific isa dma channel (called non-expansion mode) are not supported.
82443MX pciset 98 7.7.1.2 distributed dma distributed dma is a more recent scheme that has been implemented in a number of peripherals from other companies. it is based on a state machine that monitors cpu accesses to the 8237. if the accesses are associated with dma channels that are "distributed" (in some pci peripheral), then the state machine collects or distributes the data before letting the cpu complete its accesses. therefore, the cpu is accessing registers that are not located in the 440mx. 7.7.2 configuration a 16-bit configuration register is included in function 0 configuration space at offset 90h. this register is divided into seven 2-bit fields that are used to configure the seven dma channels. the remaining two bits are reserved. each dma channel can be configured to one of the following three options:  standard x-bus dma using the standard x-bus dreq/dack# signals (00)  pc/pci style dma using the req/gnt signals (01)  distributed dma (10) it is not possible for a particular dma channel to be configured for more than one type of dma, however the seven channels can be programmed independently. for example, channel 3 can be configured for pc/pci and channel 5 can be configured for distributed dma. additional configuration is required separately for the pc/pci and distributed dma functions. the 440mx does not support the pc/pci non-expansion mode. 7.7.3 pc/pci 7.7.3.1 overview the 440mx supports one pair of pc/pci reqa#/gnta#. the 440mx does not support pci bus master expansion. 7.7.3.2 additional configuration after the appropriate bits are set in register 90h, the 440mx decodes the incoming requests on the req[a]# signal. however, if the corresponding req#/gnt# signals are configured as general-purpose inputs (see register b0 in function 0), then the serial requests are never decoded. 7.7.3.3 pc/pci expansion protocol the pci expansion agent must support the pci expansion channel passing protocol for both the req# and gnt# pins as shown in figure 15.
82443MX pciset 99 pciclk start ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 bit0 bit1 bit2 start req# gnt# dma_s_ch figure 15. dma serial channel passing protocol the requesting device must encode the channel request information as shown above, where ch0Cch7 are one clock active high states representing dma channel requests 0C7. the 440mx encodes the granted channel on the gnt# line as shown above, where the bits have the same meaning as shown in figure 15. for example, the sequence [start, bit 0, bit 1, bit 2]=[0,1,0,0] grants dma channel 1 to the requesting device, and the sequence [start, bit 0, bit 1, bit 2]=[0,0,1,1] grants dma channel 6 to the requesting device. all pci dma expansion agents must use the channel passing protocol as described, and must function according to one of the following three cases: 1. if a pci dma expansion agent has more than one request active, it must resend the request serial protocol after one of the requests has been granted the bus and it has completed its transfer. the expansion device should drive its req# inactive for two clo cks and then transmit the serial channel passing protocol again, even if there are no new requests from the pci expansion agent to the 440mx. for example: if a pci expansion agent has active requests for dma channel 1 and channel 5, it passes this information to the 440mx through the expansion channel passing protocol. if after receiving gnt# (assume for ch5) and having the device finish its transfer (device stops driving request to pci expansion agent) it then must re-transmit the expansion channel passing protocol to inform the 440mx that dma channel 1 is still requesting the bus, even if that is the only request the expansion device has pending. 2. if a pci dma expansion agent has a request go inactive before the 440mx asserts gnt#, it must resend the expansion channel passing protocol to update the 440mx with this new request information. for example: if a pci expansion agent has dma channel 1 and 2 requests pending it sends them serially to the 440mx using the expansion channel passing protocol. if, however, dma channel 1 goes inactive into the expansion agent before the expansion agent receives a gnt# from the 440mx, the expansion agent must pull its req# line high for one clock and resend the expansion channel passing information with only dma channel 2 active. note that the 440mx does not do anything special in this case because dreq# going inactive before dack# is received is not allowed in the isa dma protocol and, therefore, does not need to work properly in this protocol either. this requirement is needed to support plug-n-play isa devices that toggle dreq# lines to determine if those lines are free in the system. 3. if a pci expansion agent has sent its serial request information and receives a new dma request before receiving gnt# the agent must resend the serial request with the new request active. for example: if a pci expansion agent has already passed requests for dma channels 1 and 2 and sees dma channel 3 active before gnt# is received, the device must pull its req# line high for one clock and resend the expansion channel passing information with all three channels active.
82443MX pciset 100 these three cases require the following pci dma expansion device functionality:  drive req# inactive for one clock to signal new request information.  drive req# inactive for two clocks to si gnal that a request that had been granted to the bus has gone inactive.  the req# and gnt# state machines must run independently and concurrently (i.e., gnt# could be received while in the middle of sending a serial req#, or gnt# could be active while req# is inactive). note: gnt# is associated with a retryd cycle. the 440mx does not start frame# until the encoded gnt# has been completely sent. 7.7.3.4 pc/pci expansion cycles the 440mx supports the mobile pc/pci dma protocol for the following four types of cycles: memory-to-i/o, i/o-to-memory, verify, and isa master cycles. isa masters are supported through the use of a dma channel that has been programmed for cascade mode. single transfer mode is implicitly supported as the case where the dma controller negates the dack#/gnt# signal after one transfer has been completed or the dma controller toggles dack# after every transfer. single transfer mode does not require the requesting device to negate dreq# after a cycle has completed. therefore, a pci dma agent that uses this mode must also sample the gnt# signal and remove dack# to the i/o dma device when gnt# goes inactive. the dma controller performs a two-cycle transfer (a load followed by a store), as opposed to the isa fly-by cycle for pc/pci dma agents. the memory portion of the cycle generates a pci memory read or memory write bus cycle, with its address representing the selected memory. the i/o portion of the dma cycle generates a pci i/o cycle to one of four i/o addresses (see table 61). note that these cycles must be qualified by an active gnt# signal to the requesting device. table 61. dma cycle vs. i/o address dma cycle type dma i/o address tc (a2) pci cycle type normal 00h 0 i/o read/write normal tc 04h 1 i/o read/write verify 0c0h 0 i/o read verify tc 0c4h 1 i/o read for pci dma cycles, the i/o address indicates the current dma cycle type (whether it is a normal or a verify cycle, and if this is the last transfer of the buffer). note that the a2 address line is encoded as the terminal count signal for pci cycles; a2 asserted during a pci i/o cycle indicates the last transfer in the current dma buffer. to ensure that non-mobile pc/pci compliant pci i/o devices do not confuse mobile pc/pci dma cycles for normal i/o cycles, the addresses used by the pci dma cycles correspond to the slave addresses of the mobile pc/pci dma controller. all pci dma i/o ports must be dword-aligned and can be either byte or word in size. this means that any pci dma i/o port must always be connected to the lower data lines of the pci data bus (see table 62). the byte enables also reflect this during the i/o portion of a pci dma cycle. table 63 illustrates the byte enable state for any given pci dma cycle.
82443MX pciset 101 table 62. pci data bus vs. dma i/o port size pci dma i/o port size pci data bus connection byte ad[7:0] word ad[15:0] table 63. dma i/o cycle width vs. be[3:0]# be[3:0]# dma i/o cycle width 1110b 8 bits 1100b 16 bits note: for verify cycles, the value of the byte enables (be#s) is a dont care. every dma device (including secondary bus arbiters) must recognize a valid signal on its gnt# combined with the dma i/o address as its command authorization to initiate a dma access cycle. the 440mx is required to assert the dma i/o devices gnt# signal until the data phase of the i/o portion of the dma transfer. 7.7.4 dstributed dma 7.7.4.1 overview the distributed dma scheme is based on the concept that the registers associated with individual dma can physically reside outside of the 440mx, specifically on other pci devices. the distributed dma logic in the 440mx is only used when the cpu performs accesses to the 8237 registers data movement is the responsibility of the peripheral. separate algorithms are followed depending whether the cpu attempts a read cycle or write cycle. each is covered separately. the 440mx is able to determine if a particular dma channel is "distributed" based on the pci configuration space. 7.7.4.2 additional configuration the 440mx contains two registers to indicate the i/o locations for the relocated dma registers for the ddma peripherals. the first register indicates the offset of the registers associated with dma channels 0-3. the second indicates the offset of the registers associated with dma channels 5-7. channel 4 is assumed to be unavailable, the pointers require that the registers for channels 0 and 5 start on a 64-byte boundary. channels 1 and 6 appear 16 bytes above 0 and 5. channels 2 and 7 appear 32 bytes above channels 0 and 5. channel 3 appears 48 bytes above channel 0. the bios or other configuration software is responsible for programming the ddma peripherals to the corresponding locations. during alt access mode, the write-only registers become readable, and the read-only registers become writeable. this allows a mobile bios to save and restore the state of the dma controller for proper resumption from suspend. it is assumed that during alt access mode read and write cycles, the ddma logic is not used.
82443MX pciset 102 7.7.4.3 read/write cycle protocols for read cycles on the pci bus that correspond to distributed dma channels, the 440mx performs the following algorithm: 1. the 440mx issues a pci retry to terminate this cycle. 2. the 440mx requests the pci bus. upon being granted access to the bus, the 440mx performs one or more read cycles to the 8237 and/or the peripherals. the i/o location of the read cycle is calculated based on several parameters: the ddma base pointer registers in the pci configuration space, the dma channel number (0-3, 5-7), and the register location (0h-fh). 3. the 440mx uses the data obtained via the read cycles (along with the value in the 8237) to construct the proper data value. 4. when the cpu retries the cycle, the 440mx responds with the proper data value. for write cycles on the pci bus that correspond to distributed dma channels, the 440mx performs the following algorithm: 1. the 440mx issues a pci retry to terminate this cycle. 2. the 440mx requests the pci bus. upon being granted access to the bus, the 440mx performs one or more write cycles to the 8237 and/or the peripherals. the i/o location of the write cycle is calculated based on several parameters: the ddma base pointer registers in the pci configuration space, the dma channel number (0-3, 5-7), and the register location (0h-fh). 3. the 440mx uses the data obtained via the cpu's original write cycles to determine the proper values to write to the peripherals and to the 8237. 4. when the cpu retries the cycle, the 440mx allows it to complete normally. table 64 specifies the number of read cycles (and merging format) and the number of write cycles (and data format) for each of the 8237 registers.
82443MX pciset 103 table 64. 8237 registers and ddma function register algorithm base address since each dma channel has a separate x-bus address for the base address register, the 440mx must perform one 16-bit write cycle via pci. the data value originally written by the cpu is written to the peripheral. for dma channels 0-3, the 8237 base address registers are mapped to isa 0000h, 0002h, 0004h, and 0006h. for dma channels 5-7, the 8237 base address registers are mapped to isa 00c4h, 00c8h, and 00cch. channel 4 is always assumed to be inside the 440mx. since the 8237 does not permit read accesses to the base address registers the ddma does not need to permit them. for power-management purposes, the 440mx permits reading these registers via the alt access mode. base word count since each dma channel has a separate x-bus address for the base word count register, the 440mx must perform one 16-bit write cycle via pci. the data value originally written by the cpu is written to the peripheral. for dma channels 0-3, the 8237 base word count registers are mapped to isa 0001h, 0003h, 0005h, and 0007h. for dma channels 5-7, the 8237 base word count registers are mapped to isa 00c6h, 00cah, and 00ceh. channel 4 is always assumed to be inside the 440mx. since the 8237 does not permit read accesses to the base word count registers, the ddma does not need to permit them. for power-management purposes, the 440mx permits reading these registers via the alt access mode. page since each dma channel has a separate x-bus address for the page register, the 440mx must perform one 16-bit read or write cycle via pci. the data value originally written by the cpu is written to the peripheral. for dma channels 0-3, the 8237 page registers are mapped to isa 0087h, 0083h, 0081h, and 0082h. for dma channels 5-7, the 8237 page registers are mapped to isa 008bh, 0089h, and 008ah. channel 4 is always assumed to be inside the 440mx. current address since each dma channel has a separate x-bus address for the current address register, the 440mx performs one 16-bit read cycle via pci. for dma channels 0-3, the 8237 current address registers are mapped to isa 0000h, 0002h, 0004h, and 0006h. for dma channels 5-7, the 8237 current address registers are mapped to 00c4, 00c8, and 00cch. current word count since each dma channel has a separate isa address for the current address register, the 440mx performs one 16-bit read cycle via pci. for dma channels 0-3, the 8237 current word count registers are mapped to isa 0001h, 0003h, 0005h, and 0007h. for dma channels 5-7, the 8237 current word count registers are mapped to 00c6, 00ca, and 00ceh.
82443MX pciset 104 register algorithm temporary address since the 8237 does not permit read accesses to the base address register, the ddma does not need to perform them. for power-management purposes, the 440mx permits reading this register via the alt access mode. temporary word count since the 8237 does not permit read accesses to the base address register, the ddma does not need to perform them. for power-management purposes, the 440mx permits reading this register via the alt access mode. status the status register (one for each 8237) reports the tc status and dma request status for the four channels associated with each 8237. for dma channels 0-3, the 8237 status register is mapped to isa 0008h. the 440mx must perform up to four read cycles. for dma channels 5-7, the 8237 status register is mapped to isa 00d0h. the 440mx must perform up to three read cycles. channel 4 is always assumed to be inside the 440mx. for read cycles, the 440mx assembles the status register as follows: bits 0 and 4 from channel 0 (or channel 4 if from the 2nd 8237) bits 1 and 5 from channel 1 (or channel 5 if from the 2nd 8237) bits 2 and 6 from channel 2 (or channel 6 if from the 2nd 8237) bits 3 and 7 from channel 3 (or channel 7 if from the 2nd 8237) command the command register sets various configuration options. for dma channels 0-3, the 8237 command register is mapped to isa 0008h. the 440mx must perform up to four write cycles. for dma channels 5-7, the 8237 command register is mapped to isa 00d0h. the 440mx must perform up to three write cycles. channel 4 is always assumed to be inside the 440mx. during write cycles, the 440mx copies the cpu's write value to all distributed channels. temporary the distributed dma protocol does not support memory-to-memory transfers. the distributed dma logic should let this cycle pass to the 8237 and complete normally. mode the mode register sets various configuration options. because the low two bits of the mode register are used to identify one of the four channels, only one pci write cycle is required. for dma channels 0-3, the 8237 mode register is mapped to isa 000bh. for dma channels 5-7, the 8237 mode register is mapped to isa 00d6h. channel 4 is always assumed to be inside the 440mx. during write cycles, the 440mx copies the cpu's write value to the distributed channel. single channel the single channel mask register sets or resets the mask of a single channel. because the low two bits of the mode register are used to identify one of the four
82443MX pciset 105 register algorithm mask channels, only one pci write cycle is required. for dma channels 0-3, the 8237 single channel mask register is mapped to isa 000ah. for dma channels 5-7, the 8237 single channel mask register is mapped to isa 00d4h. channel 4 is always assumed to be inside the 440mx. during write cycles, the 440mx copies the cpu's write value to the distributed channel. write all masks the multi-channel mask register simultaneously controls the ma sks for all c hannels in the 8237. for dma channels 0-3, the 8237 write all ma sks register is m apped to isa 000fh. the 440mx must perform up to four write cycles. for dma channels 5-7, the 8237 command register is mapped to isa 00deh. the 440mx must perform up to three write cycles. channel 4 is always assumed to be inside the 440mx. during write cycles, the 440mx copies the cpu's write value to all distributed channels. request the request register allows software to emulate a dma request. because the low two bits of the mode register are used to identify one of the four channels, only one pci write cycle is required. for dma channels 0-3, the 8237 request register is mapped to isa 0009h. for dma channels 5-7, the 8237 request register is mapped to isa 00d2h. channel 4 is always assumed to be inside the 440mx. during write cycles, the 440mx copies the cpu's write value to the distributed channel. software command: clear first/last flip-flop the clear first/last flip-flop command permits software to deterministically access the low or high bytes of 16-bit fields. because the peripherals do not need this, this command does not need to be written to the pci bus. software command: master clear the master clear command resets the dma controller. for dma channels 0-3, the 8237 master clear command is mapped to isa 000dh. the 440mx must perform up to four write cycles. for dma channels 5-7, the 8237 status register is mapped to isa 00dah. the 440mx must perform up to three write cycles. channel 4 is always assumed to be inside the 440mx. during write cycles, the 440mx copies the cpu's write value to the distributed channel, although the data value is a "don't care".
82443MX pciset 106 register algorithm software command: clear mask the clear mask command clears all ma sks in the dma controller. for dma channels 0-3, the 8237 clear mask command is mapped to isa 000eh. the 440mx must perform up to four write cycles. for dma channels 5-7, the 8237 status register is mapped to isa 00dch. the 440mx must perform up to three write cycles. channel 4 is always assumed to be inside the 440mx. during write cycles, the 440mx copies the cpu's write value to the distributed channel, although the data value is a "don't care." 7.7.4.4 calculating the i/o address when the 440mx attempts to access a pci peripheral, it performs i/o read or write cycles. this section describes how to calculate the exact i/o address. bits 31-16 are don't care because peripherals ignore these bits for i/o cycles. for the 440mx, these bits are set to 0. bits 15-6 are indicated by the base pointer in the pci config space for function 0. the base pointer at function 0 offset 92h is used for dma channels 0-3. the base pointer at function 0 offset 94h is used for dma channels 5-7. bits 5-4 are determined by the dma channel number being accessed as follows: dma channel number bits 5:4 000 1 or 5 01 2 or 6 10 3 or 7 11 bits 3-0 are determined by the register being accessed. note: the ddma peripheral mapping is not the same as in the 8237. table 65 shows the mapping of the 8237 register to the distributed dma peripheral. table 65. mapping the 8237 register to ddma peripheral i/o address 8237 f/f status r/w 8237 register name "distributed" cycle i/o address 0, 2, 4, or 6h, c4, c8, or cch 0 w base address register a0-7 base pointer + channel # + 0h 0, 2, 4, or 6h, c4, c8, or cch 0 r current address register a0-7 base pointer + channel # + 0h 0, 2, 4, or 6h, c4, c8, or cch 1 w base address register a8-15 base pointer + channel # + 1h
82443MX pciset 107 i/o address 8237 f/f status r/w 8237 register name "distributed" cycle i/o address 0, 2, 4, or 6h, c4, c8, or cch 1 r current address register a8-15 base pointer + channel # + 1h 87h, 83, 81, 82h 8b, 89, 8ah x r/w page register base pointer + channel # + 2h 1, 3, 5, or 7h, c6, ca, ceh 0 w base word count register d0- 7 base pointer + channel # + 4h 1, 3, 5, or 7h, c6, ca, ceh 0 r current word count register d0-7 base pointer + channel # + 4h 1, 3, 5, or 7h, c6, ca, ceh 1 w base word count register d8-15 base pointer + channel # + 5h 1, 3, 5, or 7h, c6, ca, ceh 1 r current word count register d8-15 base pointer + channel # + 5h 08h d0h x w command register base pointer + channel # + 8h 08h d0h x r status register base pointer + channel # + 8h 09h d2h x w request register base pointer + channel # + 9h 0bh d6h x w mode register base pointer + channel # + bh 0dh dah x w master clear base pointer + channel # + dh 0fh deh x w write all masks register base pointer + c hannel # + fh ah d4h x w single channel mask see the single channel mask register comment. 0eh dch x w clear mask register see the clear mask register comment. comment: single channel mask register to facilitate peripheral implementation, the distributed dma specification does not have the peripherals implement the single channel mask registers. instead, a write to the single channel mask register (which encodes the channel number in the low two bits) causes a write to occur to the write all ma sks register (which has a separate mask bit for each channel). the distributed dma peripheral uses bit 0 in the write all masks register for that particular c hannel. thus, when a write occurs to the single channel mask register, the 440mx examines the low two data bits to determine the dma channel number. this causes a write to the peripheral at base pointer + channel # + fh. the data value (bit 0) for that write cycle is determined by data bit 2 of the original cpu write.
82443MX pciset 108 comment: clear mask register to facilitate peripheral implementation, the distributed dma specification does not have the peripherals implement the clear mask command. instead, a write to the clear mask command register (which has a don't care data value) causes writes to all the distributed channels associated with that 8237. thus, when a write occurs to the clear mask command register, the 440mx performs up to four writes to the write all masks register (base pointer + c hannel # + fh) with a data value of 0h. 7.7.4.5 power management implications when the system powers down and resumes, it may need to read and later restore values associated with the dma controller. system-level restriction: peripherals using the distributed dma protocol with the 440mx must ensure all register values are readable and restorable. if the system software attempts to read a shared register, and one of the distributed channels is powered down, then an smi# must be generated to wake up the peripherals. after the read of the register, another smi# must be generated to again reduce the power. note: smi# is caused by the 440mx receiving a master abort (because the slave does not generate a devsel# within the required time). if the p4ma_en bit (bit 4) in the glbl_en register is set, then the master abort causes the smi#. 7.7.4.6 other clarifications if another pci master attempts to read or write to one of the dma controller registers, that cycle is retried until the pc dma protocol completes. this prevents two outstanding requests. if the 440mx should experience a pci time-out when attempting to read or write to a peripheral (as part of the distributed dma protocol), then the normal target abort indicator goes active in the device status register in the pci configuration space. 7.8 timer the timer block integrates one 82c54 timer/counter. 7.8.1 counter/timers the 440mx contains three counters that are equivalent to those found in the 82c54 programmable interval timer (see table 66). the three counters are contained in one timer unit, referred to as timer-1. each counter output provides a key system function. counter 0 is connected to interrupt controller irq0 and provides a system timer interrupt for a time-of-day, diskette time-out, or other system timing functions. counter 1 generates a refresh request signal and counter 2 generates the tone for the speaker. the 14.31818 mhz counters normally use osc as a clock source. full details of this counter can be found in the 82c54 data sheet .
82443MX pciset 109 table 66. interval timer functions counter function description counter 0 - system timer gate always on clock in 1.193 mhz (osc divide down) out int-1 irq0 counter 1 - refresh request gate always on clock in 1.193 mhz (osc divide down) out refresh request counter 2 - speaker tone gate programmable - port 61h clock in 1.193 mhz (osc divide down) out speaker 7.8.1.1 counter 0, system timer this counter functions as the system timer by controlling the state of irq0 and is typically programmed for mode 3 operation. the counter produces a square wave with a period equal to the product of the counter period (838 ns) and the initial count value. the counter loads the initial count value one counter period after software writes the count value to the counter i/o address. the counter initially asserts irq0 and decrements the count value by two each counter period. the counter negates irq0 when the count value reaches 0. it then reloads the initial count value and again decrements the initial count value by two each counter period. the counter then asserts irq0 when the count value reaches 0, reloads the initial count value, and repeats the cycle, alternately asserting and negating irq0. 7.8.1.2 counter 1, refresh request signal this counter provides the refresh request signal and is typically programmed for mode 2 operation. the counter negates the refresh request for one counter period (838 ns) during each count cycle. the initial count value is loaded one counter period after being written to the counter i/o address. the counter initially asserts the refresh request, and negates it for 1 counter period when the count value reaches 1. the counter then asserts the refresh request and continues counting from the initial count value. 7.8.1.3 counter 2, speaker tone this counter provides the speaker tone and is typically programmed for mode 3 operation. the counter provides a speaker frequency equal to the counter clock frequency (1.193 mhz) divided by the initial count value. the speaker must be enabled by a write to port 061h (see nmi status and control ports). 7.8.2 interval timer address map table 67. interval timer counters i/o address map i/o address register description
82443MX pciset 110 040h system timer (counter 0) 041h refresh request (counter 1) 042h speaker tone (counter 2) 043h control word register 7.8.3 programming the interval timer the counters/timers are programmed by i/o accesses and are addressed as though they are contained in one 82c54 interval timer. the interval timer is an i/o-mapped device. a single control word register controls the operation of all three counters. this section describes the several commands available for programming the interval timer. the control word command specifies the following:  counter to read or write  operating mode  count format (binary or bcd) the counter latch command latches the current count so that it can be read by the system. the countdown process continues. the read back command reads the count value, programmed mode, the current state of the out pins, and the state of the null count flag of the selected counter. the read/write logic selects the control word register during an i/o write when address lines ha[1:0]=11. this condition occurs during an i/o write to port address 043h, the address for the control word register on timer 1. if the cpu writes to port 043h, the data is stored in the control word register and is interpreted as the control word used to define the operation of the counters. the control word register is write-only. counter status information is available with the read back command. table 68 lists the six operating modes for the interval counters.
82443MX pciset 111 table 68. counter operating modes mode function 0 out signal on end of count (=0) 1 hardware retriggerable one-shot 2 rate generator (divide by n counter) 3 square wave output 4 software triggered strobe 5 hardware triggered strobe because the timer counters wake up in an unknown state after power up, multiple refresh requests may be queued. to avoid possible multiple refresh cycles after power up, program the timer counter immediately after power up. 7.8.3.1 write operations to program the interval timer follow this simple procedure: 1. write a control word. 2. write an initial count for each counter. 3. load the least and/or most significant bytes (as required by control word bits 5, 4) of the 16-bit counter. the programming procedure for the 440mx timer is very flexible. only two conventions need to be observed. first, for each counter, the control word must be written before the initial count is written. second, the initial count must follow the count format specified in the control word (least significant byte only, most significant byte only, or least significant byte and then most significant byte). since the control word register and the three counters have separate addresses (selected by the a1, a0 inputs), and each control word specifies the counter it applies to (sc0, sc1 bits), no special instruction sequence is required. any programming sequence that follows the conventions above is acceptable. a new initial count may be written to a counter at any time without affecting the counter's programmed mode. counting is affected as described in the mode definitions. the new count must follow the programmed count format. if a counter is programmed to read/write two-byte counts, the following precaution applies: a program must not transfer control between writing the first and second byte to another routine that also writes to that same counter. otherwise, the counter is loaded with an incorrect count. 7.8.3.2 interval timer control word format the control word specifies the counter, the operating mode, the order and size of the count value, and whether it counts down in a 16-bit or binary-coded decimal (bcd) format. after writing the control word, a new count may be written at any time. the new value takes effect according to the programmed mode.
82443MX pciset 112 if a counter is programmed to read/write two-byte counts, the following precaution applies: a program must not transfer control between writing the first and second byte to another routine that also writes into that same counter. otherwise, the counter is loaded with an incorrect count. the count must always be completely loaded with both bytes. 7.8.3.2.1 read operations the 440mx timer unit allows the value of a counter to be read without disturbing the count in progress. the following sections describe the three possible methods for reading the counters: a simple read operation, the counter latch command, and the read-back command. 7.8.3.2.2 counter i/o port read this method performs a simple read operation. to read the counter, which is selected with the a1, a0 inputs (port 040h, 041h, or 042h), the clk input of the selected counter must be inhibited by using either the gate input or external logic. otherwise, the count may be in the process of changing when it is read, giving an undefined result. when reading the count value directly, follow the format programmed in the control register: read lsb, read msb, or read lsb then msb. within the 440mx timer unit, the gate input on counter 0 and counter 1 is tied high. therefore, the direct register read should not be used on these two counters. the gate input of counter 2 is controlled through i/o port 061h. if the gate is disabled through this register, direct i/o reads of port 042h return the current count value. 7.8.3.3 counter latch command the counter latch command latches the count when the command is received. this command is used to ensure that the count read from the counter is accurate (particularly when reading a two-byte count). the count value is then read from each counter's count register as was programmed by the control register. the selected counter's output latch (ol) latches the count at the time the counter latch command is received. this count is held in the latch until it is read by the cpu (or until the counter is reprogrammed). the count is then unlatched automatically and the ol returns to "following" the counting element (ce). this allows the counters contents to be read "on the fly" without affecting the count in progress. multiple counter latch commands may be used to latch more than one counter. each latched counter's ol holds its count until it is read. counter latch commands do not affect the programmed mode of the counter in any way. the counter latch command can be used for each counter in the 440mx timer unit. if a counter is latched and then, some time later, latched again before the count is read, the second counter latch command is ignored. the count read is the count at the time the first counter latch command was issued. with either method, the count must be read according to the programmed format; specifically, if the counter is programmed for two-byte counts, two bytes must be read. the two bytes do not have to be read one right after the other. read, write, or programming operations for other counters may be inserted between them. another feature of the 440mx timer is that reads and writes of the same counter may be interleaved. for example, if the counter is programmed for two-byte counts, the following sequence is valid:
82443MX pciset 113 1. read least significant byte. 2. write new least significant byte. 3. read most significant byte. 4. write new most significant byte. if a counter is programmed to read/write two-byte counts, a program must not transfer control between reading the first and second byte to another routine that also reads from that same counter. otherwise, an incorrect count is read. 7.8.3.3.1 read back command the read back command determines the count value, programmed mode, and current states of the out pin and null count flag of the selected counter or counters. the read back command is written to the control word register, which causes the current states of the above mentioned variables to be latched. the value of the counter and its status may then be read by i/o access to the counter address. the read back command may be used to latch multiple counter output latches (ol) by setting the count# bit d5=0 and selecting the desired counter(s). this single command is functionally equivalent to several counter latch commands, one for each counter latched. each counter's latched count is held until it is read (or the counter is reprogrammed). once read, a counter is automatically unlatched. the other counters remain latched until they are read. if multiple count read back commands are issued to the same counter without reading the count, all but the first are ignored (i.e., the count that is read is the count at the time the first read back command was issued). the read back command may also be used to latch status information of selected counter(s) by setting status# bit d4=0. the status must be latched to be read. the status of a counter is accessed by a read from that counter's i/o port address. if multiple counter status latch operations are performed without reading the status, all but the first are ignored. the status returned from the read is the counter status at the time the first status read back command was issued. both count and status of the selected counter(s) may be latched simultaneously by setting both the count# and status# bits [5:4]=00. this is functionally the same as issuing two consecutive, separate read back commands. the above discussions apply here also. specifically, if multiple count and/or status read back commands are issued to the same counter(s) without any intervening reads, all but the first are ignored. if both the count and status of a counter are latched, the first read operation from that counter returns the latched status, regardless of which was latched first. the next one or two reads (depending on whether the counter is programmed for one- or two-type counts) return the latched count. subsequent reads return an unlatched count. 7.9 rtc 7.9.1 rtc overview the real time clock (rtc) module provides a battery backed-up date and time keeping device with two banks of static ram with 128 bytes each, although the first bank has 114 bytes for general purpose usage.
82443MX pciset 114 three interrupt features are available: time of day alarm with once a second to once a month range, periodic rates of 122  s to 500 ms, and end of update cycle notification. seconds, minutes, hours, days, day of week, month, and year are counted. daylight savings compensation is optional. the hour is represented in twelve or twenty-four hour format, and data can be represented in bcd or binary format. the design is meant to be functionally compatible with the motorola ms146818b. the time keeping comes from a 32.768 khz oscillating source, which is divided to achieve an update every second. the lower 14 bytes on the lower ram block have very specific functions. the first ten are for time and date information. the next four (0ah to 0dh) are registers, which configure and report rtc functions. the time and calendar data should match the data mode (bcd or binary) and hour mode (12 or 24 hour) as selected in register b. it is up to the programmer to ensure that data stored in these locations is within the reasonable value ranges and represents a possible date and time. the exception to these ranges is to store a value of c0h - ffh in the alarm bytes to indicate a dont care situation. all alarm conditions must match to trigger an alarm flag, which could trigger an alarm interrupt if enabled. the set bit of register b should be one while programming these locations to avoid clashes with an update cycle. access to time and date information is done through the ram locations. if a ram read from the 10 time and date bytes is attempted during an update cycle, the value read does not necessarily represent the true contents of those locations. any ram writes under the same conditions are ignored. 7.9.2 rtc registers and ram the rtc internal registers and ram are organized as two banks of 128 bytes each, called the standard and extended banks. the first 14 bytes of the standard bank contain the rtc time and date information along with four registers, a-d, which are used to configure the rtc. the extended bank contains a full 128 bytes of battery-backed sram, and is accessible even when the rtc module is disabled (via the rtc configuration register). all data transfers between the host cpu and the rtc is performed through registers mapped to the isa i/o space. 7.9.3 rtc update cycle an rtc update cycle occurs once a second if the set bit of register b is not asserted and the divide chain is properly configured. during this procedure, the stored time and date are incremented, overflow is checked, a matching alarm condition is checked, and the time and date are rewritten to the ram locations. to maintain compatibility with the motorola ms146818b, the update cycle starts at least 244  s after the uip bit of register a is asserted, and the entire cycle does not take more than 1,984  s to complete. the time and date ram locations (0-9) are disconnected from the external bus during this time. to avoid update and data conditions, external ram access to these locations can safely occur at two times. when an updated-ended interrupt is detected, almost 999 ms is available to read and write valid time and date data. if the uip bit of register a is detected to be low, at least 244  s passes before the update cycle begins. because the overflow conditions for leap years and daylight savings adjustments are based on more than one date or time item, the time before one of these conditions should be set (when adjusting) at least two seconds before one of these conditions to ensure proper operation. 7.9.4 rtc interrupts the real-time clock interrupt is internally routed to the 8259 and is mapped to interrupt vector 8. this interrupt is not shared with any other interrupt. irq8# from the serirq stream is ignored.
82443MX pciset 115 7.9.5 lockable ram ranges the real-time clock battery-backed ram supports two 8-byte ranges that can be enabled via the configuration space. if the configuration bits are set, the corresponding range in the ram is not readable or writeable. a write cycle to those locations has no effect. a read cycle to those locations does not return the actual location value. once enabled, this function can only be disabled by a hard reset. 7.9.6 rtc external connections 7.9.6.1 rtc crystal the rtc module requires an externally connected crystal on the rtcx1 and rtcx2 pins. 7.9.6.2 rtc battery the rtc module requires an external battery connection to maintain the rtc block while the 440mx is not powered by the system. the battery must also be connected to the 440mx via isolation diodes. this is both a chip-design requirement, as well as a ul requirement. the diode circuit allows the rtc well to be powered by the battery when system power is not available, but by the system power when it is available. this is done by setting the diode to be reverse-biased when system power is not available. 7.9.7 century rollover the year register only reports a value of 00 to 99. in the year 2000, this will roll over to 00, however this could be misinterpreted as 1900, not 2000. the newcentury_sts bit records this rollover. this bit is in the rtc well in the general purpose event1 status register (pmbase + 38, bit 12 system i/o space). when the system is in the active state and a century rollover occurs, the newcentury_sts bit is set, which causes an smi to be generated. the smi handler then che cks the newcentury_sts bit and finds it to be set, in which case, it increments the top two digits of the year (location 32h) in the rtc ram. in case the system is in the s1-s5 states, the century rollover also causes the newcentury_sts (rtc well) bit to be set. a wake event does not occur. once the system awakens (for some other reason), the bios finds the newcentury_sts bit set and generates an smi. the smi handler then changes (increments) the year byte in the rtc ram. 7.10 interrupt controller the 440mx contains an isa-compatible interrupt controller that incorporates the functionality of two 82c59 interrupt controllers. the interrupt registers control the operation of the interrupt controller and can be accessed from the pci bus via the pci i/o space. in addition, some of the registers can be accessed from the isa bus via the isa i/o space.
82443MX pciset 116 note: support is not provided for the secondary ide channel, so irq15 is no longer available externally for any other purpose. however, the serirq and pci interrupts can be steered to generate interrupt 15 to the 8259 interrupt controller. 7.10.1 interrupt controller functional description the two 82c59 interrupt controllers provided by the 440mx are cascaded so that 13 external and three internal interrupts are possible. the master interrupt controller provides irq [7:0] and the slave interrupt controller provides irq [15:8] (see figure 16). the three internal interrupts are used for internal functions only and are not available to the user. irq2 is used to cascade the two controllers together. irq0 is used as a system timer interrupt and is tied to interval timer 1, counter 0. irq13 is connected internally to ferr#. the remaining 13 interrupt lines (irq1, irq3-irq12, irq14, and irq15) are available for external system interrupts. edge or level-sense selection is programmable on an individual channel-by-channel basis. the interrupt unit also supports interrupt steering. the 440mx can be programmed to allow the four pci active low interrupts (pirqa#-pirqd#) to be internally routed to one of 11 interrupts: 3-7, 9-12, 14 or 15. the interrupt controller consists of two separate 82c59 cores. interrupt controller 1 (cntrl-1) and interrupt controller 2 (cntrl-2) are initialized separately and can be programmed to operate in different modes. the default settings are: 80x86 mode, edge sensitive (irq0-15) detection, normal eoi, non-buffered mode, special fully nested mode disabled, and cascade mode. cntrl-1 is connected as the master interrupt controller and cntrl-2 is connected as the slave interrupt controller. note that irq13 is generated internally (as part of the coprocessor error support). irq12/m is generated internally (as part of the mouse support) when bit 4 in the xbcs is set to 1. when set to 0, the standard irq12 function is provided and irq12 appears externally.
82443MX pciset 117 int (to cpu) 82c59 core controller 2 (slave) 0# 1 2 3 4 5 6 7 82c59 core controller 1 (master) 0 1 2 3 4 5 6 7 (intr) timer1 counter0 irq1 irq3 irq4 irq5 irq6 irq7 (intr) irq8# irq9 irq10 irq11 irq12 / m ferr# irq14 irq15 intcntl.drw figure 16. interrupt controller block diagram table 69 lists the i/o port address map for the interrupt registers.
82443MX pciset 118 table 69. interrupt controller register i/o port address map interrupts i/o address bits (#) register irq[7:0] 0020h 8 cntrl-1 control register irq[7:0] 0021h 8 cntrl-1 mask register irq[15:8] 00a0h 8 cntrl-2 control register irq[15:8] 00a1h 8 cntrl-2 mask register irq0, irq2, and irq13 are connected to the interrupt controllers internally, and do not appear externally. table 70 lists the typical irq functions. table 70. typical interrupt functions priority label controller typical interrupt source 1 irq0 1 interval timer 1, counter 0 out 2 irq1 1 keyboard 3-10 irq2 1 interrupt from controller 2 3 irq8# 2 real time clock 4 irq9 2 expansion bus pin b04 5 irq10 2 expansion bus pin d03 6 irq11 2 expansion bus pin d04 7 irq12/m 2 mouse interrupt 8 irq13 2 coprocessor error- ferr# 9 irq14 2 fixed disk drive controller expansion bus pin d07 10 irq15 2 expansion bus pin d06 11 irq3 1 serial port 2, expansion bus b25 12 irq4 1 serial port 1, expansion bus b24 13 irq5 1 parallel port 2, expansion bus b23 14 irq6 1 diskette controller, expansion bus b22 15 irq7 1 parallel port 1, expansion bus b21 7.10.1.1 interrupt sequence the powerful features of the interrupt controller in a microcomputer system are programmability and interrupt routine addressing capability. the latter allows direct or indirect jumping to the specific interrupt routine requested without any polling of the interrupting devices. the following list shows the interrupt sequence for
82443MX pciset 119 the intel architecture (the 8080 mode of the interrupt controller must never be selected when programming the 440mx). note: externally, the interrupt acknowledge cycle sequence appears to be different than in a traditional discrete 82c59 implementation. however, the traditional interrupt acknowledge sequence is generated within the 440mx and is an isa-compatible implementation. 1. one or more of the interrupt request lines (irqx) are raised high, setting the corresponding irr bit(s). 2. the interrupt controller evaluates these requests, and sends an intr to the cpu, if appropriate. 3. the cpu acknowledges the intr and responds with two interrupt acknowledge cycles. the second cycle is translated into a pci interrupt acknowledge cycle by the host bridge. this command is broadcast over the pci as a single cycle as opposed to the two-cycle method typically used. 4. upon receiving an interrupt acknowledge cycle from pci, the 440mx south bridge/cluster converts the single cycle into the two cycles that the internal 8259 pair can respond to with the expected interrupt vector. the cycle conversion is performed by a functional block in the 440mx interrupt controller unit. the internally generated interrupt acknowledge cycle is completed as soon as possible, as the host bus is held in wait states until the interrupt vector data is returned. each cycle appears as an interrupt acknowledge pulse on the inta# pin of the cascaded interrupt controllers. these two pulses are not observable at the 440mx periphery. 5. upon receiving the first internally generated interrupt acknowledge pulse, the highest priority isr bit is set and the corresponding irr bit is reset. the interrupt controller does not drive the data bus during this cycle. on the trailing edge of the first cycle pulse, a slave identification code is broadcast by the master to the slave on a private, internal three-bit wide bus. the slave controller uses these bits to determine if it must respond with an interrupt vector during the second inta# cycle. 6. upon receiving the second internally-generated interrupt acknowledge, the interrupt controller releases an 8-bit pointer (the interrupt vector) that the 440mx uses to complete the pci cycle in progress. the second cpu interrupt acknowledge cycle can now complete on the host bus. 7. this completes the interrupt cycle. in the aeoi mode the isr bit is reset at the end of the second interrupt acknowledge cycle pulse. otherwise, the isr bit remains set until an appropriate eoi command is issued at the end of the interrupt subroutine. if no interrupt request is present at step four of the sequence (i.e., the request was too short in duration), the interrupt controller issues an interrupt level 7. 7.10.1.2 interrupt acknowledge cycle the cpu generates an interrupt acknowledge cycle that is translated by the host bridge into a single pci interrupt acknowledge. the interrupt controller translates this command into the two inta# pulses expected by the interrupt controller subsystem. the interrupt controller uses the first interrupt acknowledge cycle to internally freeze the state of the interrupts for priority resolution. on the second interrupt acknowledge cycle, the master (cntrl-1) or slave (cntrl-2) sends a byte of data to the processor with the acknowledged interrupt code composed as shown in table 71. the byte of data released by the interrupt controller onto the data bus is referred to as the "interrupt vector.
82443MX pciset 120 table 71. content of interrupt vector byte for 80x86 system mode interrupt vector d7 d6 d5 d4 d3 d2 d1 d0 irq7,15 t7t6t5t4t31 1 1 irq6,14 t7t6t5t4t31 1 0 irq5,13 t7t6t5t4t31 0 1 irq4,12 t7t6t5t4t31 0 0 irq3,11 t7t6t5t4t30 1 1 irq2,10 t7t6t5t4t30 1 0 irq1,9 t7 t6 t5 t4 t3 0 0 1 irq0,8 t7 t6 t5 t4 t3 0 0 0 note: t7 - t3 represent the interrupt vector address (refer to the icw2 register description). 7.10.1.3 programming the interrupt controller the interrupt controller accepts the following two types of command words generated by the cpu or bus master:  initialization command words (icws)  operation command words (ocws) 7.10.1.3.1 initialization command words (icws) before normal operation can begin, each interrupt controller in the system must be initialized. in the 82c59, this is a two-to-four byte sequence. however, for the 440mx, each controller must be initialized with a four- byte sequence. this four-byte sequence is required to configure the interrupt controller correctly for 440mx implementation. this implementation is isa-compatible. the four initialization command words are referred to by their acronyms: icw1, icw2, icw3, and icw4. the base address for each interrupt controller is a fixed location in the i/o memory space, at 0020h for cntrl-1 and at 00a0h for cntrl-2. an i/o write to the cntrl-1 or cntrl-2 base address with data bit 4 equal to 1 is interpreted as icw1. for the 440mx-based x-bus systems, three i/o writes to "base address + 1" (021h for cntrl-1 and 0a0h for cntrl-2) must follow the icw1. the first write to "base address + 1" (021h/0a0h) performs icw2, the second write performs icw3, and the third write performs icw4.  icw1 starts the initialization sequence during which the following events automatically occur: 1. following initialization, an interrupt request (irq) input must make a low-to-high transition to generate an interrupt. 2. the interrupt mask register is cleared. 3. irq7 input is assigned priority 7.
82443MX pciset 121 4. the slave mode address is set to 7. 5. special mask mode is cleared and status read is set to irr.  icw2 is programmed to provide bits [7:3] of the interrupt vector that is released onto the data bus by the interrupt controller during an interrupt acknowledge. a different base [7:3] is selected for each interrupt controller. suggested default values for a typical isa system are listed in table 72.  icw3 is programmed differently for cntrl-1 and cntrl-2, and has a different meaning for each controller. for cntrl-1, the master controller, icw3 is used to indicate which irqx input line is used to cascade cntrl-2, the slave controller. within the 440mx interrupt unit, irq2 on cntrl-1 is used to cascade the intr output of cntrl-2. consequently, bit-2 of icw3 on cntrl-1 is set to a 1, and the other bits are set to 0's. for cntrl-2, icw3 is the slave identification code used during an interrupt acknowledge cycle. cntrl- 1 broadcasts a code to cntrl-2 over three internal cascade lines if an irq[x] line from cntrl-2 won the priority arbitration on the master controller and was granted an interrupt acknowledge by the cpu. cntrl-2 compares this identification code to the value stored in icw3, and if the code is equal to bits [2:0] of icw3, cntrl-2 assumes responsibility for broadcasting the interrupt vector during the second interrupt acknowledge cycle pulse.  icw4 must be programmed on both controllers. at the very least, bit 0 must be set to 1 to indicate that the controllers are operating in an intel architecture-based system. table 72 lists the typical values programmed by the bios at power-up for the 440mx interrupt controller. figure 17 illustrates the sequence the software must follow to load the icws. the sequence must be executed for cntrl-1 and cntrl-2. icw1, icw2, icw3, and icw4 must be written in order. any divergence from this sequence, such as an attempt to program an ocw, will result in improper initialization of the interrupt controller and unexpected, erratic system behavior. it is suggested that cntrl-2 be initialized first, followed by cntrl-1. in the 440mx, it is required that all four icws be initialized. table 72. suggested default values for icw registers port value contents 020h 11h cntlr-1, icw1 021h 08h cntlr-1, icw2 vector address for 000020h 021h 04h cntlr-1, icw3 indicates slave connection 021h 01h cntlr-1, icw4 8086 mode 021h b8h cntlr-1, interrupt mask (may vary) 0a0h 11h cntlr-2, icw1 0a1h 70h cntlr-2, icw2 vector address for 0001c0h 0a1h 02h cntlr-2, icw3 indicates slave id 0a1h 01h cntlr-2, icw4 8086 mode 0a1h bdh cntlr-2, interrupt mask (may vary)
82443MX pciset 122 icw 3 is ic w 4 needed? icw 4 ready to accept interrupt requests yes (ic4=1) yes (sngl=0) icw2 in cascade mode? sio-04.drw icw 1 cntrl-1 cntrl-2 i/o address special conditions 020h 0a0h d 4 = 1 021h 0a1h m u s t im m e d ia te ly fo llo w icw 2 access 021h 0a1h m u s t im m e d ia te ly fo llo w icw 1 access 021h 0a1h m u s t im m e d ia te ly fo llo w icw 3 access figure 17. initialization sequence for the 440mx icw modes of operation 7.10.1.3.2 operation command words (ocws) ocws are command words that dynamically reprogram the interrupt controller to operate in various interrupt modes. ocws can be written to the interrupt controller any time after initialization. the three operation command words are referred to by their acronyms: ocw1, ocw2, and ocw3.  any interrupt lines can be masked by writing an ocw1. a 1 written to any bit of this command word masks the incoming interrupt r equests on the corresponding irqx line.
82443MX pciset 123  ocw2 is used to control the rotation of interrupt priorities when operating in the rotating priority mode and to control the end of interrupt (eoi) function of the controller.  ocw3 is used to set up reads of the isr and irr, to enable or disable the special mask mode (smm), and to set up the interrupt controller in polled interrupt mode. as shown in figure 17, all icws must be programmed prior to programming the ocws. 7.10.1.4 end-of-interrupt operation 7.10.1.4.1 end of interrupt (eoi) the in service (is) bit can be set to 0 automatically following the trailing edge of the second inta# pulse (when aeoi bit in icw1 is set to 1) or by a command word that must be issued to the interrupt controller before returning from a service routine (eoi command). an eoi command must be issued twice with this cascaded interrupt controller configuration, once for the master and once for the slave. there are two forms of eoi commands: specific and non-specific. when the interrupt controller is operated in modes that preserve the fully nested structure, it can determine which is bit to set to 0 on eoi. when a non-specific eoi command is issued, the interrupt controller automatically sets to 0 the highest is bit of those that are set to 1, since in the fully nested mode the highest is level was necessarily the last level acknowledged and serviced. a non-specific eoi can be issued with ocw2 (eoi=1, sl=0, r=0). when a mode is used that may disturb the fully nested structure, the interrupt controller may no longer be able to determine the last level acknowledged. in this case, a specific eoi must be issued which includes as part of the command the is level to be reset. a specific eoi can be issued with ocw2 (eoi=1, sl=1, r=0, and lo-l2 is the binary level of the is bit to be set to 0). it should be noted that an is bit that is masked by an imr bit will not be cleared by a non-specific eoi if the interrupt controller is in the special mask mode. 7.10.1.4.2 automatic end of interrupt (aeoi) mode if aeoi=1 in icw4, then the interrupt controller operates in aeoi mode continuously until reprogrammed by icw4. note that reprogramming icw4 implies that icw1, icw2, and icw3 must be reprogrammed first, in sequence. in aeoi mode, the interrupt controller automatically performs a non-specific eoi operation at the trailing edge of the last interrupt acknowledge pulse. note that from a system standpoint, this mode should be used only when a nested multi-level interrupt structure is not required within a single interrupt controller. the aeoi mode can only be used in a master interrupt controller and not a slave (on cntrl-1 but not cntrl-2). 7.10.1.4.3 fully nested mode the fully nested mode is entered after initialization unless another mode is programmed. the interrupt requests are ordered in priority from 0 through 7 (0 being the highest). when an interrupt is acknowledged, the highest priority request is determined and its vector placed on the bus. additionally, a bit in the interrupt service register (is[0:7]) is set. this is bit remains set until the microprocessor issues an end of interrupt (eoi) command immediately before returning from the service routine. or, if the aeoi (automatic end of interrupt) bit is set, this is bit remains set until the trailing edge of the second inta#. while the is bit is set, all further interrupts of the same or lower priority are inhibited, while higher levels generate an interrupt (which is acknowledged only if the microprocessor internal interrupt enable flip-flop has been re-enabled through software).
82443MX pciset 124 after the initialization sequence, irq0 has the highest priority and irq7 the lowest. priorities can be changed in the rotating priority mode, as explained later in this section. 7.10.1.4.4 the special fully nested mode this mode is used in the case of a system where cascading is used, and the priority has to be conserved within each slave. in this case, the special fully nested mode is programmed to the master (using icw4). this mode is similar to the normal nested mode with the following exceptions:  when an interrupt request from a certain slave is in service, this slave is not locked out from the master's priority logic and further interrupt requests from higher priority irqs within the slave are recognized by the master and initiate interrupts to the processor. (in the normal nested mode, a slave is masked out when its request is in service and no higher requests from the same slave can be serviced.)  when exiting the interrupt service routine, the software must check whether the interrupt serviced was the only one from that slave. this is done by sending a non-specific end of interrupt (eoi) command to the slave and then reading its in-service register and checking for zero. if it is empty, a non-specific eoi can also be sent to the master. if not, no eoi should be sent. 7.10.1.4.5 automatic rotation (equal priority devices) in some applications, a number of interrupting devices have equal priority. automatic rotation mode provides for a sequential 8-way rotation. in this mode, a device receives the lowest priority after being serviced. in the worst case, a device requesting an interrupt must wait until each of seven other devices are serviced at most once. figure 18 illustrates an example of automatic rotation. if the priority and "in service" status is: after rotate (irq4 was serviced, all other priorities rotated correspondingly) 2 107654 3 priority status h ighest priority is7 is6 is5 is4 is3 is2 is1 is0 0 1000000 "is" status lowest priority sio-05.drw 7 6543210 priority status lowest priority highest priority before rotate (irq4 the highest priority requiring service) is7 is6 is5 is4 is3 is2 is1 is0 0 1 01 0 000 "is" status figure 18. automatic rotation mode example
82443MX pciset 125 there are two ways to accomplish automatic rotation using ocw2; the rotation on non-specific eoi command (r=1, sl=0, eoi=1) and the rotate in automatic eoi mode which is set by (r=1, sl=0, eoi=0) and cleared by (r=0, sl=0, eoi=0). 7.10.1.4.6 specific rotation (specific priority) the programmer can change priorities by programming the bottom priority and thus fixing all other priorities. for example, if irq5 is programmed as the bottom priority device, then irq6 is the highest priority device. the set priority command is issued in ocw2 where: r=1, sl=1; lo-l2 is the binary priority level code of the bottom priority device. see the register description for bit definitions. note that, in this mode, internal status is updated by software control during ocw2. however, it is independent of the end of interrupt (eoi) command (also executed by ocw2). priority changes can be executed during an eoi command by using the rotate on specific eoi command in ocw2 (r=1, sl=1, eoi=1 and lo-l2=irq level to receive bottom priority). 7.10.1.4.7 poll command the polled mode can be used to conserve space in the interrupt vector table. multiple interrupts that can be serviced by one interrupt service routine do not need separate vectors if the service routine uses the poll command. the polled mode can also be used to expand the number of interrupts. the polling interrupt service routine can call the appropriate service routine, instead of providing the interrupt vectors in the vector table. in this mode, the intr output is not used and the microprocessor internal interrupt enable flip-flop is reset, disabling its interrupt input. service to devices is achieved by the software using a poll command. the poll command is issued by setting p=1 in ocw3. the interrupt controller treats the next i/o read pulse to the interrupt controller as an interrupt acknowledge, sets the appropriate is bit if there is a request, and reads the priority level. interrupts are frozen from the i/o write to the i/o read. figure 19 shows the words enabled onto the data bus during an i/o read. the polled mode is useful if there is a routine command common to several levels so that the inta# sequence is not needed (saves rom space). 1---- -- --w2w1w0 d7 d6 d5 d4 d3 d2 d1 d0 sio-06.drw notes: w0-w2: binary code of the highest priority level requesting service. bit d7 i: equal to 1 if there is an interrupt. figure 19. polled mode
82443MX pciset 126 7.10.1.4.8 cascade mode the interrupt controllers in the 440mx are interconnected in a cascade configuration with one master and one slave. this configuration can handle up to 15 separate priority levels. the master controls the slaves through a three-line internal cascade bus. when the master drives 010b on the cascade bus, this bus acts like a chip select to the slave controller. in a cascade configuration, the slave interrupt outputs are connected to the master interrupt request inputs. when a slave request line is activated and afterwards acknowledged, the master enables the corresponding slave to release the interrupt vector address during the second inta# cycle of the interrupt acknowledge sequence. each interrupt controller in the cascaded system must follow a separate initialization sequence and can be programmed to work in a different mode. an eoi command must be issued twice: once for the master and once for the slave. 7.10.1.4.9 edge and l evel triggered mode in x-bus systems this mode is programmed using bit 3 in icw1. with the 440mx this bit is disabled and a new register for edge and level triggered mode selection, per interrupt input, is included. these are the edge/level control registers elcr1 and elcr2. the default programming is equivalent to programming the ltim bit (icw1 bit 3) to a 0 (all interrupts selected for edge triggered mode). note that irq0, 1, 2, 8#, and 13 cannot be programmed for level sensitive mode and cannot be modified by software. if an elcr bit = "0", an interrupt request is recognized by a low-to-high transition on the corresponding irqx input. the irq input can remain high without generating another interrupt. if an elcr bit = "1", an interrupt request is recognized by a low level on the corresponding irq input and there is no need for an edge detection. the interrupt request must be removed before the eoi command is issued to prevent a second interrupt from occurring. in both the edge and level triggered modes, the irq inputs must remain active until after the falling edge of the first inta#. if the irq input goes inactive before this time, a default irq7 occurs when the cpu acknowledges the interrupt. this can be a useful safeguard for detecting interrupts caused by spurious noise glitches on the irq inputs. to implement this feature, the irq7 routine is used for "clean up" by simply executing a return instruction, and thus ignoring the interrupt. if irq7 is needed for other purposes, a default irq7 can still be detected by reading the isr. a normal irq7 interrupt sets the corresponding isr bit; a default irq7 does not set this bit. if a default irq7 routine occurs during a normal irq7 routine, however, the isr remains set. in this case, it is necessary to keep track of whether or not the irq7 routine was previously entered. if another irq7 occurs, it is a default. 7.10.1.5 register functionality for a detailed description of the interrupt controller register set, refer to the interrupt controller register description in the register description section.
82443MX pciset 127 7.10.1.6 interrupt masks 7.10.1.6.1 masking on an individual interrupt request basis each interrupt request input can be masked individually by the interrupt mask register (imr). this register is programmed through ocw1. each bit in the imr ma sks one interrupt channel, if it is set to a 1. bit 0 masks irq0, bit 1 masks irq1, and so forth. masking an irq channel does not affect the other channel's operation, with one exception: masking irq2 on cntrl-1 ma sks off all r equests for service from cntrl-2. the cntrl-2 intr output is physically connected to the cntrl-1 irq2 input. 7.10.1.6.2 special mask mode some applications may require an interrupt service routine to dynamically alter the system priority structure during its execution under software control. for example, the routine may wish to inhibit lower priority requests for a portion of its execution but enable some of them for another portion. the difficulty is that if an interrupt request is acknowledged and an end of interrupt command did not reset its is bit (i.e., while executing a service routine), the interrupt controller would have inhibited all lower priority requests with no easy way for the routine to enable them. the special mask mode enables all interrupts not masked by a bit set in the mask register. interrupt service routines that require dynamic alteration of interrupt priorities can take advantage of the special mask mode. for example, a service routine can inhibit lower priority requests during a part of the interrupt service, then enable some of them during another part. in the special mask mode, when a mask bit is set to 1 in ocw1, it inhibits further interrupts at that level and enables interrupts from all other levels (lower as well as higher) that are not masked. thus, any interrupts may be selectively enabled by loading the mask register with the appropriate pattern. without special mask mode, if an interrupt service routine acknowledges an interrupt without issuing an eoi to clear the is bit, the interrupt controller inhibits all lower priority requests. the special mask mode provides an easy way for the interrupt service routine to selectively enable only the interrupts needed by loading the mask register. special mask mode is set by ocw3 where: ssmm=1, smm=1, and cleared where ssmm=1, smm=0. 7.10.1.7 reading the interrupt controller status the input status of several internal registers can be read to update the user information on the system. the interrupt request register (irr) and in-service register (isr) can be read via ocw3. the interrupt mask register (imr) is read via a read of ocw1. this section briefly describes irr, isr, and imr.  interrupt request register (irr): this 8-bit register that contains the status of each interrupt request line. bits that are clear indicate interrupts that have not requested service. the interrupt controller clears the irr's highest priority bit during an interrupt acknowledge cycle. (not affected by imr).  in-service register (isr): this 8-bit register indicates the priority levels currently receiving service. bits that are set indicate interrupts that have been acknowledged and their interrupt service routine started. bits that are cleared indicate interrupt requests that have not been acknowledged, or interrupt request lines that have not been asserted. only the highest priority interrupt service routine executes at any time. the lower priority interrupt services are suspended while higher priority interrupts are serviced. the isr is updated when an end of interrupt command is issued.
82443MX pciset 128  interrupt mask register (imr): this 8-bit register indicates which interrupt request lines are masked. the irr can be read when, prior to the i/o read cycle, a read register command is issued with ocw3 (rr=1, ris=0). the isr can be read when, prior to the i/o read cycle, a read register command is issued with ocw3 (rr=1, ris=1). the interrupt controller retains the isr/irr status read selection following each write to ocw3. therefore, there is no need to write an ocw3 before every status read operation, as long as the current status read corresponds to the previously selected register. for example, if the isr is selected for status read by an ocw3 write, the isr can be read over and over again without writing to ocw3 again. however, to read the irr, ocw3 must be reprogrammed for this status read prior to the ocw3 read to check the irr. this is not true when poll mode is used. polling mode overrides status read when p=1, rr=1 in ocw3. after initialization the interrupt controller is set to read the irr. as stated, ocw1 is used to read the imr. the output data bus contains the imr status whenever i/o read is active and the address is 021h or 061h (ocw1). 7.10.1.8 interrupt steering the 440mx can be programmed to allow four pci programmable interrupts (pirqa#-pirqd#) to be internally routed to one of 11 interrupts: 3-7, 9-12, 14 or 15. pclk is used to synchronize the pirqx# inputs. the pirqx# lines are run through an internal multiplexer that assigns, or routes, an individual pirqx# line to any one of 11 irq inputs (see figure 20 for an illustration of the interrupt steering logic). the assignment is programmable through the pirqx route control registers. one or more pirqx# lines can be routed to the same irqx input. if interrupt steering is not required, the route registers can be programmed to disable steering. bits 0-3 in each pirqx route control register are used to route the associated pirqx# line to an internal irq input. bit 7 in each register is used to disable routing of the associated pirqx#. the pirqx# lines are defined as active low, level sensitive to allow multiple interrupts on a pci board to share a single line across the connector. when a pirqx# is routed to specified irq line, the software must change the irq's corresponding elcr bit to level sensitive mode. this means that the selected irq can no longer be used by an x-bus device, unless that x-bus device can respond as an active low level sensitive interrupt.
82443MX pciset 129 pirq# irq15 irq14 irq11 irq10 pi rqx# contr ol regis ters irq13 ir q7 irq6 ir q5 ir q4 ir q3 ir q1 timer/counter 82c59 82c59 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 mbirq control registers ir q0 inv irq12/m ir q9 irq8# sync decoder (abcd) 4 figure 20. section of interrupt steering logic (without serial irq)
82443MX pciset 130 7.10.2 serial irq scheme for more information about the serial irq scheme, see the serialized irq support for pci systems , rev 6.0. 7.10.2.1 overview the 440mx supports a serial irq scheme that allows a single signal to be used to report isa-style interrupt requests. this scheme is typically used in a mobile environment by docking bridges or cardbus controllers. because more than one device may need to share the single serial irq signal, an open collector signaling scheme is used. timing is based on the pci clock. if the pci clock is shut when a device needs to signal an interrupt, the clkrun# signal must first be activated to restart the pci clock. the serial irq configuration is handled via the pci configuration space. no other registers are associated with the scheme. 7.10.2.2 protocol serial interrupt information is transferred using three frame types: a start frame, one or more irq data frames, and one stop frame. there are also two modes of operation: quiet mode and continuous mode. 7.10.2.2.1 quiet (active) mode to indicate an interrupt, the peripheral drives the serirq signal active for one clock, and then three-states it. this transitions all state machines from the idle to active states. the 440mx then takes control of the serirq signal by driving it low on the next clock, and continues driving it low for 3-7 more clocks (programmable). thus the total number of clocks serirq is low is 4-8. after those clocks, the 440mx drives serirq high for one clock and then three-states the signal. 7.10.2.2.2 continuous (idle) mode in this mode, the 440mx initiates the start frame, rather than the peripherals. typically this is done to update the irq status (acknowledges). the 440mx drives serirq low for 4-8 clo cks. this is the default mode after reset, and can be used to enter the quiet mode. 7.10.2.2.3 data frame after the start frame is initiated, all serirq peripherals must start counting frames based on the rising edge of serirq. each of the irq/data frames has exactly three phases of 1 clock each: a sample phase, a recovery phase, and a turn-around phase. during the sample phase, the serirq device drives serirq low if the corresponding interrupt signal should be active. if the corresponding interrupt is inactive, then the serirq devices should not drive the serirq signal. it remains high due to pull-up resistors. note: the 440mx ignores the state of the irq0 signal. this may preclude using a timer/counter chip outside of the 440mx. however, that configuration is not supported by any previous intel pciset.
82443MX pciset 131 during the other two phases (turn-around and recovery), no device should drive the serirq signal. the irq/data frames have a specific order and usage, as shown in table 73. table 73. sirq frames data frame number usage # clocks past start notes 1 irq0 2 not supported by the 440mx. 2irq15 3 smi# 8 causes exsmi# to go active 4irq311 5irq414 6irq517 7irq620 8irq723 9irq826 10 irq9 29 11 irq10 32 12 irq11 35 13 irq12 38 14 irq13 41 15 irq14 44 16 irq15 47 17 iochck# 50 not supported 18 pci inta# 53 supported 19 pci intb# 56 supported 20 pci intc# 59 supported 21 pci intd# 62 supported 22-32 unassigned 96 not supported the 440mx is not required to broadcast internal interrupt states. this greatly reduces the amount of transitions on the serirq signal and simplifies the state machine.
82443MX pciset 132 7.10.2.2.4 stop frame after all of the data frames, the 440mx performs a stop frame, which is done by making serirq low for 2-3 clocks. the number of clocks determines the next m ode:  if serirq is low for 2 clocks, t hen the next mode is the quite mode. any seriirq device may initiate a start frame in the second clock (or more) after the rising edge of the stop frame.  if serirq is low for 3 clocks, t hen the next mode is the continuous mode. only the 440mx may initiate a start frame in the second clock (or more) after the rising edge of the stop frame. 7.10.2.3 smi# via serirq when an smi# is indicated via serirq, the 440mx drives its exsmi# signal active. this in turn causes smi# to go active. the bios sees exsmi# go active, with no corresponding status bit set in the peripheral. the bios can then check the devices connected to the serirq signal to find the cause of the smi#. 7.10.2.4 serirq oring with isa irq the 440mx internally ors the output of the serirq decoder with the isa irq signals. the pnp software should ensure that two separate devices are not programmed to use the same isa irq signals, unless the drivers are set up for interrupt sharing. otherwise, this could result in unpredictable operation, and is already a system limitation. 7.11 usb host controller the 440mx contains a usb host controller (hc), which includes a root hub with two usb ports. this permits connection of two usb peripheral devices directly to the 440mx without an external hub. if more devices are required, an external hub can be connected to either of the built-in ports. the usbs pci configuration registers are located in function 2, pci configuration space. the host controller completely supports the standard universal host controller interface (uhci) and thus, takes advantage of the standard software drivers written to be compatible with uhci. figure 21 shows a conceptual view of a usb system. uhci consists of two partshost controller driver (hcd) and host controller (hc). the host controller interfaces to the usb system software in the host via the hcd. the hcd software manages the host controller operation and is responsible for scheduling the traffic on usb by posting and maintaining transactions in system memory. hcd is part of the system software and is typically provided by the operating system vendor. hcd provides the software layer between the host controller and the usbd software layer (also located in the operating system). the uhcis hcd software interprets requests from the usbd and builds frame list, transfer descriptor, queue head, and data buffer data structures for the host controller. the data structures are built in system memory and contain all necessary information to provide end-to-end communication between client software in the host and devices on the usb. the host controller moves data between system memory and devices on the usb by processing these data structures and generating the transaction on the usb. the host controller executes the schedule lists generated by the hcd and reports the status of transactions on the usb to the hcd. command execution includes generating serial bus token and data packets based on the command and initiating transmission on usb. for commands that require the host controller to receive data from the usb device, the host controller receives the data and then transfers it to the system memory pointed to by the command. the uhcis hcd provides sufficient commands and data to keep ahead of the host controller execution and analyzes the results as the commands are completed.
82443MX pciset 133 for additional information on the functionality of the usb host controller, refer to the universal host controller interface (uhci) design guide , revision 1.1 (order number 297650-002). note that the uhci design guide refers to usb ports 1 and 2. the 440mx usb ports are ports 0 and 1, respectively. additions to the 440mx usb interface beyond uhci, revision 1.1 include support for over-current detection on usb ports 0 and 1. if an over-current condition is detected on a usb port, that port will be disabled. bits 10:11 in each port status and control register are used to report over-current conditions. client software universal serial bus driver (usbd) universal host controller driver (hcd) universal host controller (hc) usb device usb device usb usb universal host controller interface (uhci) hardware software usb_blk figure 21. usb system conceptual view 7.12 ide interface the 440mx integrates a high performance pci-to-ide interface, which has one physical channel adapter and supports two drives (drive 0 and drive 1) this interface is capable of accelerated pio data transfers as well as acting as a pci bus master on behalf of an ide dma slave device. the 440mx provides an interface for a single ide connector. all ide data transfer command strobes, dma request and grant signals, address and data lines, and the piordy signal interface directly to the 440mx. these lines correspond to the primary ide channel. only pci masters have access to the ide port. memory targeted by the ide interface acting as a pci bus master on behalf of ide dma slaves must reside on the pci or in the main memory implemented by the 440mx.
82443MX pciset 134 although a physical secondary ide channel interface does not exist on the 440mx, all of the configuration i/o ports still exist and are claimed, if enabled, by the 440mx. the bios is expected to disable this channel. the 440mx does not support swap bay. 7.12.1 ata register block decode the ide ata i/o ports are decoded by the 440mx when the com[iose] bit is set to one, as well as idetimp[ide] and idetims[ide]. (ata stands for "at attachment", the specification for at-compatible drive interfaces). the actual ata registers are implemented in the drive itself. an access to an ide register results in the assertion of the appropriate chip select for that register. the transaction is then run using compatible timing, and using the ide command strobes (pdior#, pdiow#). there are two i/o ranges: the command block, which corresponds to the cs1# chip select, and the control block, which corresponds to the cs3# chip select. the command block is an 8-byte range, while the control block is a 4-byte range. the upper 16 bits of the i/o address are decoded as all zeros. command block offset: 01f0h for primary, 0170h for secondary control block offset: 03f4h for primary, 0374h for secondary table 74 and table 75 specify the command block and control block registers, respectively, as they affect the 440mx hardware definition. see the at attachment specification for more details. table 74. ide legacy i/o ports: command block registers (cs1x# chip select) i/o offset register function (read / write) register access 00h data r/w 01h error / features r/w 02h sector count r/w 03h sector number r/w 04h cylinder low r/w 05h cylinder high r/w 06h drive / head r/w 07h status / command r/w the data register is accessed as a 16-bit register for pio transfers (except for ecc bytes). all other registers should always be accessed as 8-bit quantities by software. table 75. ide legacy i/o port definition: control block registers (cs3x# chip select) i/o offset register function (read / write) register access 00h reserved reserved 01h reserved reserved 02h alt status / device control r/w
82443MX pciset 135 03h forward to x-bus (floppy) r/w
82443MX pciset 136 the 440mx claims all accesses to these ranges, if enabled. the byte enables do not have to be externally decoded to assert devsel#. accesses to byte 3 of the control block are forwarded to the x-bus, where the floppy controller responds. a 16-bit access to offset 02h of the control block (byte enables 2 and 3 asserted) results in a target abort. each of the two drives (drive 0 or 1) on a cable implements separate ata register files. to determine the targeted drive, the 440mx shadows the value of bit 4 (drive bit) of byte 6 (drive/head register) of the ata command block (cs1x#) for the ide connector. 7.12.2 pio ide transactions the 440mx ide controller includes both compatible and fast timing modes. the fast timing modes can be enabled only for the ide data ports. all other transactions to the ide registers are run in single transaction mode with compatible timings. the 440mx ide signals are controlled with the granularity of the pci clock. up to two ide devices may be attached to the ide connector (drive 0 and drive 1). the idetim and sidetim registers permit different timing modes to be programmed for drive 0 and drive 1 of the connector. the ultra dma/33 synchronous dma timing modes can also be applied to each drive by programming the sdmactl and sdmatim registers. when a drive is enabled for synchronous dma mode operation, the dma transfers are executed with the synchronous dma timings. the pio transfers are executed using compatible timings or fast timings if also enabled. 7.12.3 pio ide timing modes ide data port transaction latency consists of startup latency, cycle latency and shutdown latency. startup latency is incurred when a pci master cycle targeting the ide data port is decoded and the pda[2:0] and csxx# lines are not set up. startup latency provides the setup time for the pda[2:0] and csxx# lines prior to assertion of the read and write strobes (pdior# and pdiow#). cycle latency consists of the i/o command strobe assertion length and recovery time. recovery time is provided so that transactions may occur back-to-back on the ide interface (without incurring startup and shutdown latency) without violating the minimum cycle periods for the ide interface. the command strobe assertion width for the enhanced timing mode is selected by the idetim register and may be set to 2, 3, 4, or 5 pci clocks. the recovery time is selected by the idetim register and may be set to 1, 2, 3, or 4 pci clocks. figure 22 shows how these latencies are related, and how they are summed to produce the overall transaction latency. figure 23 illustrates the case where the piordy sample point (isp) is set to two clocks (minimum) and the recovery time (rct) is set to one clock (minimum).
82443MX pciset 137 valid and stable pclk pda[2:0], csxx# pdiox# startup latency cycle period shutdown latency piordy sample point recovery time piordy sample point [isp] [rct] [isp] figure 22. enhanced ide timing mode components pclk piordy pdiox# a b a b b piordy sample point (isp) recovery time (rct) wait states figure 23. inserting wait states by de-asserting piordy if piordy is asserted when the initial sample point is reached, no wait states are added to the command strobe assertion length. if piordy is negated when the initial sample point is reached, additional wait states are added. since the rising edge of piordy must be synchronized, at least two additional pci clo cks are added. shutdown latency is incurred after outstanding scheduled ide data port transactions (either a non-empty write post buffer or an outstanding read prefetch cycle) have completed and before other transactions can proceed. it provides hold time on the pda[2:0] and cxxx# lines with respect to the read and write strobes (pdior# and pdiow#). shutdown latency is 2 pci clocks in duration. table 76 shows the timings for various ide transactions. it is important to note that the icrt (isa controller recovery timer) register (config register 4ch) does not affect the ide data ports when fast timing modes are enabled. specifically, setting bit 2 (16-bit i/o recovery enable) should not add wait states to ide data port read accesses when any of the fast timing modes are enabled. table 76. command strobe width for ide transaction types ide transaction type startup latency isp rct shutdown latency 30-33 mhz non data port (8- bit) 411222 30-33 mhz data port (16-bit) 3 6 14 2
82443MX pciset 138 enhanced timing data port 2 2-5 1-4 2 note: command strobe widths are in pci clock units. note: startup and recovery latencies are incurred for all ide pio transactions, except enhanced timing data port transactions. further, the ide chip selects are guaranteed to be de-asserted for at least two clocks after the de-assertion of the i/o str obe for the last transaction and before the startup latency of the next. 7.12.4 enhanced timing modes the ide interface implemented by the 440mx includes fast timing modes that target local bus implementations. these timing modes are faster than those possible with isa-based implementations and are controlled with the granularity of the pci clock. the fast timing modes may be enabled only for the ide data ports. all other transactions to the ide registers are run in single transaction mode with compatible timings. up to two ide devices may be attached to the ide connector (drive 0 and drive 1). the timing mode for the drives is selected via several registers. when the idetimx[sitre] bit is disabled, one fast timing mode can be applied to one or both drives by programming the idetimx[isp] and idetimx[rct] fields as shown in table 77. fast timing mode may be applied to drive 0, drive 1, or both, by setting the idetimx[time0] and/or the idetimx[time1] bits. transactions targeting the other drive use compatible timing. when the idetimx[sitre] bit is enabled, a fast timing mode can be selected for each drive by programming the idetimx and sidetim registers. table 77 identifies how these bits can be programmed for drive 0 and drive 1 timing mode selection. table 77. idetimx timing modes for drives 0 and 1 idetimx [sitre] idetimx [time0] idetimx [time1] drive 0 timing drive 1 timing 0 0 0 compatible compatible 0 0 1 compatible idetimx[isp/rct] 0 1 0 idetimx[isp/rct] compatible 0 1 1 idetimx[isp/rct] idetimx[isp/rct] 1 0 0 compatible compatible 1 0 1 compatible sidetim[isp/rct] 1 1 0 idetimx[isp/rct] compatible 1 1 1 idetimx[isp/rct] sidetim[isp/rct] the synchronous dma timing mode can also be applied independently to each drive by programming the sdmac and sdmatim registers. when a particular drive is programmed for sync dma mode (syncdma and sdmatim registers) and a fast timing mode (idetimx or sidetim register), dma transfers are processed using the sync dma timing mode and pio transfers are processed using the fast timing mode.
82443MX pciset 139 7.12.4.1 piordy masking when the idetimx[ie0] or idetimx[ie1] bits are 0 the external piordy signal is ignored and the internal piordy signal is assumed asserted at the first isp sample point. 7.12.4.2 pio 32-bit ide data port accesses a 32-bit pci transaction run to the ide data address results in two back-to-back 16-bit transactions to the ide data port. the 32-bit data port feature is enabled for all timings, not just enhanced timing. for compatible timings, a shutdown and startup latency is incurred between the two 16-bit halves of the ide transaction. this guarantees that the chip selects will be negated for at least two pci clo cks betw een the two cycles. 7.12.4.3 pio ide data port prefetching and posting the 440mx can be programmed via the idetim registers to allow data to be posted to and prefetched from the ide data ports. data prefetching is initiated when a data port read occurs. the read prefetch eliminates latency to the ide data ports and allows them to perform back-to-back for the highest possible pio data transfer rates. the first data port read of a sector is called the demand read. subsequent data port reads from the sector are called prefetch reads. the demand read and all prefetch reads must be of the same size (16 or 32 bits). data posting is performed for writes to the ide data ports. the transaction is completed on the pci bus after the data is received by the 440mx. the 440mx then runs the ide cycle to transfer the data to the drive. if the 440mx write buffer is non-empty and an unrelated (non-data) ide transaction occurs, that transaction will be stalled until all current data in the write buffer is transferred to the drive. 7.12.5 bus master function the ide interface integrated in the 440mx can act as a pci bus master on behalf of an ide slave device. by performing an ide data transfer as a pci bus master, the 440mx off-loads the cpu and improves system performance in multitasking environments. 7.12.5.1 physical region descriptor format the physical memory region to be transferred during a data transfer is described by a physical region descriptor (prd). the prds are stored sequentially in a descriptor table in memory. the data transfer proceeds until all regions described by the prds in the table have been transferred. note that the 440mx bus master ide function does not support memory regions or descriptor tables located on the x-bus. descriptor tables must be aligned on 64-kbyte boundaries. each prd entry in the table is eight bytes in length. the first four bytes specify the byte address of a physical memory region, which must be dword- aligned and cannot cross a 64-kbyte boundary. the next two bytes specify the size or transfer count of the region in bytes (64-kbyte limit per region). a value of zero in these two bytes indicates 64k (thus the minimum transfer count is 1). if bit 7 (eot) of the last byte is a 1, it indicates that this is the final prd in the descriptor table. bus master operation terminates when the last descriptor has been retired. figure 24 illustrates the physical region descriptor table entries.
82443MX pciset 140 byte 3 byte 2 byte 1 byte 0 memory region physical base address [31:1] dword 0 dword 1 eol reserved byte count [15:1] memory region figure 24. physical region descriptor table entry note: when the bus master ide controller is reading data from the memory regions, bit 1 of the base address is masked and byte enables are asserted for all read transfers. the controller reads to a boundary of 64 bytes, regardless of the byte count field of the prd. however, only the byte count value is transferred to the drive. when writing data, bit 1 of the base address is not masked and if set, causes the lower word byte enables to be negated for the first dword transfer. the write to pci typically consists of a 32-byte cache line. if valid data ends prior to the end of the cache line, the byte enables are negated for invalid data. the total sum of the byte counts in every prd of the descriptor table must be equal to or greater than the size of the disk transfer request. if greater than the disk transfer request, the driver must terminate the bus master transaction (by setting bit 0 in the bus master ide command register to 0) when the drive issues an interrupt to signal transfer completion. 7.12.5.2 operation to initiate a bus master transfer between memory and an ide dma slave device, the following steps are required: 1. software prepares a prd table in system memory. each prd is eight bytes long and consists of an address pointer to the starting address and the transfer count of the memory buffer to be transferred. in any given prd table, two consecutive prds are offset by eight bytes and are aligned on a four-byte boundary. 2. software provides the starting address of the prd table by loading the prd table pointer register. the direction of the data transfer is specified by setting the read/write control bit. clear the interrupt bit and error bit in the status register. 3. software issues the appropriate dma transfer command to the disk device. this includes the total amount of data to be transferred. 4. engage the bus master function by writing a '1' to the start bit in the bus master ide command register. the first entry in the prd table is fetched and loaded into the current base and current count registers. the channel remains masked until the first descriptor is loaded. 5. the controller transfers data to/from memory responding to dma requests from the ide device. when the last data transfer for a memory region has been completed on the ide interface, the next prd is
82443MX pciset 141 fetched from the table. the controller then begins transferring data to or from that prds memory region. 6. the ide device signals an interrupt once its programmed data count has been transferred. the ide device also negates its dma request signal, causing the 440mx to stop transferring data. if the 440mx has also transferred the final data from the last prd memory region, it will reset the bmidea bit in the status register and mask the dma request signal from the drive. 7. in response to the interrupt, the software resets the start/stop bit in the command register. it then reads the controller status followed by the drive status to determine if the transfer completed successfully. 7.12.6 ultra dma/33 synchronous dma operation ultra dma/33 is a physical protocol used to transfer data between an ultra dma/33 capable ide controller such as the 440mx and one or more ultra dma/33 capable ide devices. it utilizes the standard bus master ide functionality and interface to initiate and control the transfers. ultra dma/33 utilizes a source synchronous signaling protocol to transfer data at rates up to 33 mbytes/second. the ultra dma/33 definition also incorporates a cyclic redundancy checking (crc-16) error checking protocol. crc-16 only has the ability for detecting errors, not correcting them. 7.12.6.1 signal descriptions table 78 lists the ide signals that are redefined for sync dma protocol implementation. table 78. ultra dma/33 control signal redefinition standard ide signal definition ultra dma/33 read cycle definition ultra dma/33 write cycle definition 440mx channelsignal pdiow# stop stop pdiow# pdior# dmardy# strobe pdior# piordy strobe dmardy# piordy pdiow# is redefined as stop for both read and write transfers. this is always driven by the 440mx and is used to request that a transfer be stopped or as an acknowledgment to stop a request from an ide device. pdior# is redefined as dmardy# for transferring data from the ide device to the 440mx (read). it is used by the 440mx to signal when it is ready to transfer data and to add wait states to the current transaction. pdior# is redefined as strobe for transferring data from the 440mx to the ide device (write). it is the data strobe signal driven by 440mx on which data is transferred during each rising and falling edge transition. the piordy signal is redefined as strobe for transferring data from the ide device to the 440mx (read). it is the data strobe signal driven by the ide device on which data is transferred during each rising and falling edge transition. piordy is redefined as dmardy# for transferring data form the 440mx to the ide device (write). it is used by the ide device to signal when it is ready to transfer data and to add wait states to the current transaction. all other signals on the ide connector retain their functional definitions during ultra dma/33 operation.
82443MX pciset 142 7.12.6.2 operation initial setup programming consists of enabling and performing the proper configuration of the 440mx and the ide device for ultra dma/33 operation. for the 440mx, this consists of enabling synchronous dma mode and setting up appropriate synchronous dma timings. when ready to transfer data to or from an ide device, the bus master ide programming model is followed. once programmed, the drive and the 440mx control the transfer of data via the ultra dma/33 protocol. the actual data transfer consists of three phases: startup, data transfer, and burst termination. the ide device begins the startup phase by asserting dmarq signal. when ready to begin the transfer, the 440mx asserts the dmack# signal. when dmack# is asserted, the host controller drives cs0# and cs1# inactive, pda[2:0] low, and the ide device drives iocs16# inactive. for write cycles, the 440mx negates stop, waits for the ide device to assert dmardy#, and then drives the first data word and strobe signal. for read cycles, the 440mx three-states the pdd lines, negates stop, and asserts dmardy#. the ide device then sends the first data word and strobe. the data transfer phase continues the burst transfers with the data transmitter (440mx writes, ide device reads) providing data and toggling strobe. data is transferred (latched by receiver) on each rising and falling edge of strobe. the transmitter can pause the burst by holding strobe high or low, resuming the burst by again toggling strobe. the receiver can pause the burst by negating dmardy# and resumes the transfers by asserting dmardy#. to prevent an internal line buffer overflow or underflow condition, the 440mx pauses the burst transaction and resumes after the condition has cleared. it may also pause a transaction if the current prd byte count has expired, resuming after it has fetched the next prd. the current burst can be terminated by either the transmitter or receiver. a burst termination consists of a stop request, stop acknowledge and transfer of crc data. a burst must first be paused (as described) before it can be terminated. the 440mx can then stop the burst by asserting stop, with the ide device acknowledging by negating dmarq. the ide device can then stop the burst by negating dmarq and the 440mx acknowledges by asserting stop. the transmitter then drives the strobe signal to a high level. the 440mx then drives the crc value on to the pdd lines and negates dmack#. the ide device latches the crc value on the rising edge of dmack#. the 440mx terminates a burst transfer if a programmed i/o (pio) cycle is executed with the ide channel currently running the burst, or upon transferring the last data from the final prd. 7.12.6.3 crc calculation cyclic redundancy checking (crc-16) is used for error checking on ultra dma/33 transfers. the crc value is calculated for all data by both the 440mx and the ide device over the duration of the ultra dma/33 burst transfer segment. this segment is defined as all data transferred with a valid strobe edge from pddak# assertion to pddak# negation. at the end of the transfer burst segment, the 440mx drives the crc value onto the pdd[15:0] signals. it is then latched by the ide device on negation of pddak#. the ide device compares the 440mx crc value to its own and reports an error if there is a mismatch. the timings for ultra dma/33 are programmed into the ultra dma/33 timing register. the programmable timings include cycle time (ct) and ready to pause (rp) time. ct represents the minimum pulse width of the active data strobe (strobe) signal. rp represents the number of pci clo cks the 440mx waits for the negation of dmardy# to the assertion of stop when it desires to stop a burst read transaction. 7.12.6.4 reference the ata synchronous dma transfer protocol (proposal) rev 0.40 written by quantum was used as a reference for the synchronous dma mode section of this specification. the reference document contains
82443MX pciset 143 protocol rules, ac timings, and example state machines for the sync dma modes. to avoid conflicts due to document revisions, the protocol rules are not duplicated in this specification. please reference the most recent revision of the reference document for protocol rules and ac timings. 7.13 x-bus the 440mx incorporates a subset of a full isa-compatible interface. the 440mx x-bus only supports 8-bit target i/o cycles and memory cycles. primary supported devices on the x-bus are sio, kbc, rom bios. the bios address space for the x-bus is 512kb (sa[18:0]). the x-bus does not support 16-bit cycles or x- bus master cycles. the x-bus interface provides i/o recovery support, wait-state generation, and sysclk generation. the x-bus is designed to interface to 3.3v or 5v peripherals residing on the main system board. all cycles intended for the x-bus are positively decoded. the x-bus provides the following support for motherboard devices:  dma between x-bus i/o devices and main memory with four dma channels (ch. 0-3). while these channels may be used by any x-bus dma device, typically three of the four channels are used by an external floppy disk controller, parallel port controller, and ir controller.  8-bit "super i/o" interface with dedicated positively decoded i/o ranges at 1-of-n legacy addresses for floppy, parallel port, and serial port.  two positive decode variable ranges for other peripherals.  keyboard controller interface with dedicated kbccs# chip select (claims addresses 60h and 64h).  two programmable i/o chip selects. the programmable ranges for these chip selects are defined in the pci configuration space. these ranges are distinct from the programmable ranges mentioned in item 3 above. these devices are assumed to be on the x-bus. the x-bus interface supports the following cycle types:  cpu-initiated i/o and memory cycles to the x-bus. cycles initiated from the external pci bus are not supported.  compatible timing dma cycles between main memory and x-bus i/o. dma cycles are shown and described in section 7.6. 7.13.1 target i/o interface the 440mx executes x-bus i/o cycles as an x-bus master whenever a cpu-initiated i/o cycle is targeted to the x-bus. figure 25 illustrates the i/o cycle timings supported by the 440mx. as an x-bus master, the 440mx executes compressed cycles whenever zerows# is detected asserted.
82443MX pciset 144 0ns 250ns 500ns 750ns zerows# iochrdy ior#/iow# a a b c d e e a b c d c d d e d b sysclk notes: a. 8-bit compressed i/o (@ 3 sysclks) b. 8-bit compressed i/o (@ 4 sysclks) c. 8-bit compressed i/o (@ 5 sysclks) d. 8-bit standard i/o (@ 6 sysclks) e. 8-bit extended i/o (@ 7 sysclks) figure 25. isa 8-bit i/o cycles 7.13.2 x-bus clock (sysclk) generation the 440mx generates the x-bus system clock, sysclk. sysclk is based on a divide-by-4 of pciclk and has a frequency of 8.25 mhz, based on a pciclk frequency of 33 mhz. sysclk may be stretched to speed up accesses to the x-bus. when the 440mx stops pciclk, it also stops sysclk. 7.13.3 wait state and shortened cycle generation the 440mx adds wait states during i/o target cycles to the x-bus if iochrdy is sampled de-asserted. wait states are added as long as iochrdy is low. the 440mx shortens the i/o target cycles (not including dma) if zerows# is sampled active. note: if iochrdy is sampled de-asserted and zerows# is sampled asserted simultaneously, the iochrdy level takes precedence and wait states will be added.
82443MX pciset 145 7.13.4 i/o recovery the i/o recovery mechanism in the 440mx is used to add additional recovery delay between consecutive cpu-originated cycles to the x-bus. the 440mx automatically forces a minimum delay of 3.5 sysclks between back-to-back i/o cycles to the x-bus (see exception below) . this delay is measured from the rising edge of the first i/o command (ior# or iow#) to the falling edge of the next i/o command. if a delay of greater than 3.5 sysclks is required by the peripheral, the x-bus i/o recovery time register at configuration register 4ch in device #7, function 0 can be programmed to increase the delay in increments of sysclks. exception: no i/o recovery delay is inserted for back-to-back i/o "sub-cycles" generated as a result of byte assembly or disassembly. 7.14 system management bus (smbus) the system management bus (smbus) is a two-wire interface through which the system can communicate with simple power-related chips. with smbus, a device can provide manufacturer information, indicate its model/part number, save its state for a suspend event, report different types of errors, accept control parameters, and return status. the 440mx provides an smbus host controller, host controller slave port, and two smbus slave shadow ports (see figure 26). the smbus host controller provides a mechanism for the processor to initiate communications with smbus peripherals. this can be used to configure system devices or to query devices for status. the smbus slave interface provides a mechanism for other smbus masters to communicate with the 440mx and can be used to generate interrupts or resume events for a suspended system. the 440mx also supports the smbus alert# protocol. the 440mx smbus controller has 3.3v input buffers, which requires the systems smbus to be designed with a 3.3v termination voltage. the programming model is split between function 3 pci configuration registers and smbus i/o space registers. the system management bus is a subset of the philips* i 2 c* protocol. 7.14.1 smbus host interface an smbus host controller is used to send commands to various smbus devices. the 440mx smbus controller implements a full host controller implementation. the 440mx smbus controller supports the following seven command protocols of the smbus interface (see the system management bus specification , revision 1.0 ):  quick command  send byte  receive byte  write byte/word  read byte/word  block read  block write
82443MX pciset 146 smbus host controller smbus slave interface - host slave - shadow p smbus figure 26. 440mx smbus interfaces to execute an smbus host transaction, the type of transfer protocol, the address of smbus device, the device specific command, the data, and any control bits are first setup. then the start bit is set, which causes the host controller to execute the transaction. when the transaction completes, the 440mx generates an interrupt, if enabled. the interrupt can be selected by irq9 or smi#. the system software can wait for the interrupt to signal completion or it can monitor the host_busy status bit. an interrupt is also signaled if an error occurred during the transaction or if the transaction was terminated by the software setting the kill bit. the smbhstcnt, smbhstcmd, smbhstadd, smbhstdat0, smbhstdat1, and smbblkdat registers should not be accessed after setting the start bit while the host_busy bit is active (until transaction completion). the smbus controller does not respond to the start bit being set unless all interrupt status bits in the smbhststs register have been cleared. for block read or block write protocols, the data is stored in a 32-byte block data storage array. this array is addressed via an internal index pointer, which is initialized to zero on each read of the smbhstcnt register. after each access to the smbblkdat register, the index pointer is incremented by one. for block write transactions, the data to be transferred is stored in this array and the byte count is stored in the smbhstdat0 register prior to initiating the transaction. for block read transactions, the smbus peripheral determines the amount of data transferred. after the transaction completes, the byte count transferred is located in smbhstdat0 register and data is stored in the block data storage array. accesses to the array during execution of the smbus transaction always start at address 0. any register values needed for computation purposes should be saved prior to the starting of a new transaction, as the smbus host controller updates the registers while executing the new transaction.
82443MX pciset 147 7.14.2 smbus slave interface the 440mx supports three separate mechanisms for smbus peripherals to communicate to the 440mx. in addition to transferring data, these mechanisms can generate an interrupt or resume the system from a suspend state. the first mechanism consists of accesses to the smbus controller host slave port at address 10h. (note that this address is actually 0001 000x as this is a 7-bit address (bits[7:1]) with bit 0 being an r/w bit.) the host slave port responds to word write transactions only with the incoming data being stored in the smbslvdat register and incoming command in the smbshdwcmd register. an interrupt or resume event is generated (if enabled) if the incoming command matches the command stored in the smbslvc register and at least one bit read into the smbslvdat register matches with the corresponding bit in the smbslvevt register. the second mechanism monitors accesses to the smbus controller slave shadow ports at addresses stored in the smbshdw1 and smbshdw2 registers. the shadow slave ports responds to word write transactions only with the incoming data being stored in the smbslvdat register and incoming command being stored in the smbshdwcmd register. an interrupt or resume event is generated (if enabled) when the slave shadow ports are accessed. the slv_bsy bit indicates that the 440mx slave interface is receiving an incoming message. the smbslvcnt, smbshdwcmd, smbslvevt, smbslvdat, and smbslvc registers should not be accessed while the slv_bsy bit is active (until completion of transaction). the third method for smbus devices to communicate with the 440mx is with the smbalert# signal. when enabled and the smbalert# signal is asserted, the 440mx generates an interrupt or resumes the system from a suspend state. this simple mechanism allows a device without smbus master capabilities to request service from the smbus host (440mx). to determine which device asserted the smbalert# signal, the 440mx host controller should be programmed to execute a read command using the alert response address. once the slave interface has received a transaction and generated an interrupt, it stops responding to new requests until all interrupt status bits in the smbslvsts register are cleared. 7.15 gpio the 440mx contains 31 general-purpose input and output signals that can be used for system customization. the signals are grouped into the following two categories:  general purpose outputs (gpo) standard non three-stateable outputs  general purpose inputs (gpi) standard input depending on the general configuration, not all of the gpio signals will be available because they may be used for some other dedicated function. 7.15.1 configuration the 440mx signals are configured through the pci configuration function 0, registers b0-b3, d4-db, e0-e3. the bios must set the configuration of the signals before attempting to use them. the general signal and configuration register (device #7, function 0 pci config space) bits that affect the following gpios: reqa#, gnta#, serirq and irq8# remain in the same power plane (i.e., the core power plane). gpi_reg:32 (dev #7, function 3, power management i/o space) is in the core well and is reset by pcirst# (not rsmrst#).
82443MX pciset 148 7.16 system clocking cpu clock generator ( ck100/66-m ) apic clock generator cpu s y stem & memor y ctl usb controller cpu m g t. pci clock generator ( ck100/66-m ) ac'97 codec ac'97 controller i/o m g t. ide controller pci controller osc 8254 timer, acpi timer hclkin (2.5v, 66 mhz) pclkin ( 3.3v, 33 mhz ) usb clock generator clk48 ( 3.3v, 48 mhz ) ac_bit_clk ( 3.3v, 12.288 mhz ) cpustp# pcistp# osc ( 3.3v, 14.31818 mhz ) clock generator seg.0 & mininb c/s system clock domain pll ckbf-m dclko dclkrd, dclkwr dimm 0 dimm 1 osc rtc 32.768 khz figure 27. system clocking the smbus clock runs at ? the rtc clock rate, while the internal block of the smbus controller runs at the rtc clock rate.
82443MX pciset 149 table 79. system clocking clock domain frequency (mhz) usage hclkin 66 cpu i/f dclko 66 sdram clock pclkin 33 pci bus, ide controller clk48 48 usb ac'97 12.288 ac'97 link osc 14.31818 8254, acpi rtc 0.032768 rtc, power management hclkin c0, c1, c2 cpustp# (c3, s1-s5) dclko c0-c3, s1-s3 susc# (s4, s5) pclkin c0-c3 pcistp# (s1-s5) clk48 c0-c3 susa# (s1-s5)
82443MX pciset 150 8. pinout and package information 8.1 440mx pinout figure 28 and figure 29 show the ball footprint of the 440mx package in a top-side view and a pin-side view, respectively. these figures represent the pinout by ball number. for an alphabetical list of the pinout by signal name, refer to table 81. v0001-01 hd35# hd28# hd51# hd42# hd53# hd58# hd62# ad28 ad25 pciclk preq1# c/be2# frame# ad13 ad14 ad5 ad8 ad7 ad6 ad1 preq3#g pio29 nm i ignne# hd24# hd33# hd36# hd43# hd41# hd57# hd60# clkrun# ad29 ad26 ad20 ad30 par ad15 c/be1# ad9 ad2 ad4 c/be0# pgnt3# gpio30 a20m# intr init# ferr# hd21# hd27# vss hd34# hd49# vss hd52# hd40# pgnt1# ad31 vss ad27 ad21 ad24 ad19 ad16 ad10 vss pirqc# gpio22 gnta# gpio3 a20gate vcc sm i# ac_bit_ clk hd3# hd20# hd39# hd37# hd44# hd45# hd55# hd56# hd63# preq0# pgnt2# c/be3# ad23 ad17 ad11 irdy# serr# ad0 reqa# gpio2 pirqa# rcin# cpustp# ac_dat a_in0 ac_syn c vss hd30# hd25# hd32# hd46# hd48# hd59# hd54# hd50# pgnt0# preq2# ad22 pcirst# vcc ad18 ad12 devsel# ad3 pirqd# gpio23 pirqb# pcistp# stpclk# exsm i# gpio24 ac_dat a_in1 hd17# hd11# gtlref vss vttb irq14 gpio1 vss ac_rst# pm e# gpio0 hd12# hd22# vcc ac_sdat a_out gpio18 susa# susb# ha27# hd23# hd8# irq8# gpio6 lid gpio10 btlw# gpio11 pwr btn# hclkin ha26# hd9# ha18# gpio4 ri# gpio12 smbclk sm b data usb prt0+ vss ha20# ha23# vtta test# gpio17 gpio20 usb prt1+ vssusb ha29# ha21# ha16# vccusb usb prt0- sus_ stat# usb prt1- oc0# ha11# ha12# ha13# rsmrst# oc1# rtcx2 pwrok ha8# ha28# ha5# gpio15 pcs0# gpio19 vss vccrtc clk48 vss ha10# ha7# dreq3 gpio27 dack3# gpio28 pcs1# gpio16 zerows# gpio21 spkr gpio14 bpri# ha4# defer# kbccs# gpio26 bioscs# gpio13 sd3 iochrdy htrdy# hreq1# hreq2# mccs# gpio25 rstdrv sd6 sd2 sd7 vss hlock# drdy# dbsy# sa18 dreq2 iow# memw# memr# hit# md63 rs2# sd0 sd5 sysclk sd1 md29 md27 md28 sa12 sa17 vss sa14 md60 md30 md26 md20 dack1# ior# irq3 irq8 sa15 vss md25 md21 vcc vss piordy dack0# sa6 sa4 sa10 md59 md24 md18 md19 md16 pddak# sa8 sa5 dack2# dclko md22 md23 md17 cke3# pdcs3# sa13 sa11 sa0 ma6# tc irq1 sa2 pdd2 sa3 sa1 pdd13 gpio5 irq4 irq12 vss 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 ma11# vss ma10 ma13 md53 md48 md50 vcc md49 md51 irq7 dreq0 pdd4 pdd11 pdd1 vcc thrm# gpio8 sa16 sd4 irq5 vcc gpio9 vccsus hd38# hd47# hd61# trdy# stop# plock# refvcc serirq gpio7 we# cke0# vcc pdd9 pdd12 pdd7 pdd0 pda1 cke2# ma5# cke1# md45 md44 md40 vcc md38 md35 md33 pdd8 pdd6 pdiow# pdcs1# ma2# ma4# ma1# cs3# md46 md43 md41 md36 md34 md5 md32 pdd10 pdd5 pdd15 cs2# vss md47 dqm0 md11 vss md39 md42 md37 vss md4 pdd3 pda2 vss ma12# ma8# cs0# scas# dqm5 dqm1 md14 md13 md9 md8 md7 md2 md1 pda0 ma9# ma7# ma3# ma0# cs1# sras# dqm4 md15 md12 md10 md6 md3 md0 pdd14 a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af vcc sa7 osc vss 25 26 hd16# hd29# vss hd13# hd18# hd19# hd31# hd26# hd7# hd2# hd5# hd14# hd0# hd10# hd1# vss vcc vcc vss vcc vss vss vss vss vcc vss vss vss vss vss vss vcc vcc vss vcc vss vss vss vss vss vss vss vss vss vcc vcc vss vcc vss vcc vcc susc# susclk dreq1 sa9 hd4# hd15# vss cpurst# hd6# ha30# ha31# ha17# ha24# ha25# ha22# ha15# ha19# ha14# ha3# bnr# ha6# hreq0# ha9# hitm# hreq4# rs1# ads# hreq3# md31 rs0# breq0# md62 md61 md57 md58 md56 dclk dqm7 dqm3 dqm6 dqm2 md54 md52 vss md55 rtcx1 pddrq pdior# figure 28. 440mx pinout (top side view)
82443MX pciset 151 v0002-01 hd35# hd28# hd51# hd42# hd53# hd58# hd62# ad28 ad25 pciclk preq1# c/be2# frame# ad13 ad14 ad5 ad8 ad7 ad6 ad1 preq3#g pio29 nm i ignne# hd24# hd33# hd36# hd43# hd41# hd57# hd60# clkrun# ad29 ad26 ad20 ad30 par ad15 c/be1# ad9 ad2 ad4 c/be0# pgnt3# gpio30 a20m# intr init# ferr# hd21# hd27# vss hd34# hd49# vss hd52# hd40# pgnt1# ad31 vss ad27 ad21 ad24 ad19 ad16 ad10 vss pirqc# gpio22 gnta# gpio3 a20gate vcc sm i# ac_bit_ clk hd3# hd20# hd39# hd37# hd44# hd45# hd55# hd56# hd63# preq0# pgnt2# c/be3# ad23 ad17 ad11 irdy# serr# ad0 reqa# gpio2 pirqa# rcin# cpustp# ac_dat a_in0 ac_syn c vss hd30# hd25# hd32# hd46# hd48# hd59# hd54# hd50# pgnt0# preq2# ad22 pcirst# vcc ad18 ad12 devsel# ad3 pirqd# gpio23 pirqb# pcistp# stpclk# exsmi# gpio24 ac_dat a_in1 hd17# hd11# gtlref vss vttb irq14 gpio1 vss ac_rst# pm e# gpio0 hd12# hd22# vcc ac_sdat a_out gpio18 susa# susb# ha27# hd23# hd8# irq8# gpio6 lid gpio10 btlw# gpio11 pwr btn# hclkin ha26# hd9# ha18# gpio4 ri# gpio12 sm bclk sm b data usb prt0+ vss ha20# ha23# vtta test# gpio17 gpio20 usb prt1+ vssusb ha29# ha21# ha16# vccusb usb prt0- sus_ stat# usb prt1- oc0# ha11# ha12# ha13# rsm rst# oc1# rtcx2 pwrok ha8# ha28# ha5# gpio15 pcs0# gpio19 vss vccrtc clk48 vss ha10# ha7# dreq3 gpio27 dack3# gpio28 pcs1# gpio16 zerows# gpio21 spkr gpio14 bpri# ha4# defer# kbccs# gpio26 bioscs# gpio13 sd3 iochrdy htrdy# hreq1# hreq2# mccs# gpio25 rstdrv sd6 sd2 sd7 vss hlock# drdy# dbsy# sa18 dreq2 iow# memw# memr# hit# md63 rs2# sd0 sd5 sysclk sd1 md29 md27 md28 sa12 sa17 vss sa14 md60 md30 md26 md20 dack1# ior# irq3 irq8 sa15 vss md25 md21 vcc vss piordy dack0# sa6 sa4 sa10 md59 md24 md18 md19 md16 pddak# sa8 sa5 dack2# dclko md22 md23 md17 cke3# pdcs3# sa13 sa11 sa0 ma6# tc irq1 sa2 pdd2 sa3 sa1 pdd13 gpio5 irq4 irq12 vss ma11# vss ma10 ma13 md53 md48 md50 vcc md49 md51 irq7 dreq0 pdd4 pdd11 pdd1 vcc thrm# gpio8 sa16 sd4 irq5 vcc gpio9 vccsus hd38# hd47# hd61# trdy# stop# plock# refvcc serirq gpio7 we# cke0# vcc pdd9 pdd12 pdd7 pdd0 pda1 cke2# ma5# cke1# md45 md44 md40 vcc md38 md35 md33 pdd8 pdd6 pdiow# pdcs1# ma2# ma4# ma1# cs3# md46 md43 md41 md36 md34 md5 md32 pdd10 pdd5 pdd15 cs2# vss md47 dqm0 md11 vss md39 md42 md37 vss md4 pdd3 pda2 vss ma12# ma8# cs0# scas# dqm5 dqm1 md14 md13 md9 md8 md7 md2 md1 pda0 ma9# ma7# ma3# ma0# cs1# sras# dqm4 md15 md12 md10 md6 md3 md0 pdd14 vcc sa7 osc vss hd16# hd29# vss hd13# hd18# hd19# hd31# hd26# hd7# hd2# hd5# hd14# hd0# hd10# hd1# vss vcc vcc vss vcc vss vss vss vss vcc vss vss vss vss vss vss vcc vcc vss vcc vss vss vss vss vss vss vss vss vss vcc vcc vss vcc vss vcc vcc susc# susclk dreq1 sa9 hd4# hd15# vss cpurst# hd6# ha30# ha31# ha17# ha24# ha25# ha22# ha15# ha19# ha14# ha3# bnr# ha6# hreq0# ha9# hitm# hreq4# rs1# ads# hreq3# md31 rs0# breq0# md62 md61 md57 md58 md56 dclk dqm7 dqm3 dqm6 dqm2 md54 md52 vss md55 rtcx1 pddrq pdior# 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 25 26 a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af figure 29. 440mx pinout (pin side view) 8.2 440mx package dimensions figure 30 and figure 31 illustrate the 440mx pciset mechanical dimensions (see table 80 for dimension values) in a top/side view and a bottom view, respectively. the package is a 492 ball grid array (bga).
82443MX pciset 152 pin a1 i.d. pin a1 corner d d1 e e1 top view a a2 a1 c side view 492_pk g 1.vsd 30 figure 30. 440mx bga package dimensions (top and side view)
82443MX pciset 153 492_pkg2.vsd a b c d e f g h j k l p r t u v y ab aa ac 2 10 16 20 22 3 5 7 9 11 13 15 17 19 1 21 23 ad ae n 25 24 w 4 6 18 8 12 14 m af 26 pin a1 corner b e j l 492 bga bottom view figure 31. 440mx bga package dimensions (bottom view)
82443MX pciset 154 table 80. 440mx package dimensions symbol e = 1.27 mm (solder ball pitch) notes min (mm) nominal (mm) max (mm) a 2.17 2.38 2.59 a1 0.50 0.60 0.70 a2 1.12 1.17 1.22 b 0.60 0.75 0.90 c 0.55 0.61 0.67 d 34.80 35.00 35.20 d1 29.75 30.00 30.25 e 34.80 35.00 35.20 e1 29.75 30.00 30.25 i 1.63 ref. j 1.63 ref. m 26 x 26 matrix n4.92
82443MX pciset 155 table 81. alphabetical bga pin list signal name pin signal name pin signal name pin a20gate c4 ad20 b14 cpurst# j26 a20m# b4 ad21 c12 cpustp# d3 ac_bit_clk c1 ad22 e13 cs0# af19 ac_sdata_in0 d2 ad23 d12 cs1# ae17 ac_sdata_in1 e1 ad24 c11 cs2# ad19 ac_rst# f2 ad25 a16 cs3# ac16 ac_sdata_out g5 ad26 b15 dack0# aa4 ac_sync d1 ad27 c13 dack1# y5 ad0 d7 ad28 a17 dack2# ab1 ad1 a5 ad29 b16 dack3# / gpio28 p4 ad2 b8 ad30 b13 dbsy# u21 ad3 e7 ad31 c15 dclk ab25 ad4 b7 ads# v26 dclko ac24 ad5 a9 bioscs# r4 defer# r22 ad6 a6 bnr# r26 devsel# e8 ad7 a7 bpri# r24 dqm0 ad16 ad8 a8 breq0# w25 dqm1 af16 ad9 b9 batlow# / gpio11 h3 dqm2 ad25 ad10 c8 c/be0# b6 dqm3 ac25 ad11 d10 c/be1# b10 dqm4 ae15 ad12 e9 c/be2# a13 dqm5 af17 ad13 a11 c/be3# d13 dqm6 ad26 ad14 a10 cke0# aa18 dqm7 ac26 ad15 b11 cke1# ab17 drdy# u22 ad16 c9 cke2# ab19 dreq0 ae4 ad17 d11 cke3# ac20 dreq1 v1 ad18 e10 clk48 n1 dreq2 u4 ad19 c10 clkrun# b17 dreq3 / gpio27 p5
82443MX pciset 156 signal name pin signal name pin signal name pin exsmi# / gpio24 e2 ha18# j21 hd14# f26 ferr# b1 ha19# n25 hd15# h25 frame# a12 ha20# k23 hd16# b25 gnta# / gpio3 c5 ha21# l23 hd17# f24 gpio1 f4 ha22# m25 hd18# d25 gpio4 j5 ha23# k22 hd19# d26 gpio5 af4 ha24# l25 hd20# d23 gpio9 j6 ha25# m26 hd21# c24 gpio13 r3 ha26# j23 hd22# g22 gpio15 n5 ha27# h23 hd23# h22 gpio17 k4 ha28# n23 hd24# b24 gpio18 g4 ha29# l24 hd25# e22 gpio20 k3 ha30# k26 hd26# c26 gtlref f22 ha31# k25 hd27# c23 ha3# p25 hclkin j24 hd28# a23 ha4# r23 hd0# g24 hd29# a25 ha5# n22 hd1# g26 hd30# e23 ha6# r25 hd2# e26 hd31# b26 ha7# p22 hd3# d24 hd32# e21 ha8# n24 hd4# h26 hd33# b23 ha9# t25 hd5# f25 hd34# c21 ha10# p23 hd6# j25 hd35# a24 ha11# m24 hd7# e25 hd36# b22 ha12# m23 hd8# h21 hd37# d21 ha13# m22 hd9# j22 hd38# f19 ha14# p26 hd10# g25 hd39# d22 ha15# n26 hd11# f23 hd40# c17 ha16# l22 hd12# g23 hd41# b20 ha17# l26 hd13# c25 hd42# a21 hd43# b21 ignne# a2 ma12# af21
82443MX pciset 157 signal name pin signal name pin signal name pin hd44# d20 init# b2 ma13 af22 hd45# d19 intr b3 mccs# / gpio25 t5 hd46# e20 iochrdy r1 md0 ae9 hd47# f18 ior# y4 md1 af9 hd48# e19 iow# u3 md2 af10 hd49# c20 irdy# d9 md3 ae10 hd50# e16 irq1 ad2 md4 ad9 hd51# a22 irq3 y3 md5 ac10 hd52# c18 irq4 af3 md6 ae11 hd53# a20 irq5 w6 md7 af11 hd54# e17 irq6 y2 md8 af12 hd55# d18 irq7 ae3 md9 af13 hd56# d17 irq8# / gpio6 h5 md10 ae12 hd57# b19 irq12 af2 md11 ad15 hd58# a19 irq14 f5 md12 ae13 hd59# e18 kbccs# / gpio26 r5 md13 af14 hd60# b18 lid / gpio10 h4 md14 af15 hd61# f17 ma0# ae18 md15 ae14 hd62# a18 ma1# ac17 md16 ab20 hd63# d16 ma2# ac19 md17 ac21 hit# v23 ma3# ae19 md18 ab22 hitm# u26 ma4# ac18 md19 ab21 hlock# u23 ma5# ab18 md20 y21 hreq0# t26 ma6# ad20 md21 aa22 hreq1# t23 ma7# ae20 md22 ac23 hreq2# t22 ma8# af20 md23 ac22 hreq3# v25 ma9# ae21 md24 ab23 hreq4# u25 ma10 ae22 md25 aa23 htrdy# t24 ma11# ad21 md26 y22 md27 w22 md57 aa26 pdd6 ab8
82443MX pciset 158 signal name pin signal name pin signal name pin md28 w21 md58 aa25 pdd7 aa8 md29 w23 md59 ab24 pdd8 ab9 md30 y23 md60 y24 pdd9 aa10 md31 w24 md61 y25 pdd10 ac8 md32 ac9 md62 y26 pdd11 ae7 md33 ab10 md63 v22 pdd12 aa9 md34 ac11 memr# u1 pdd13 af7 md35 ab11 memw# u2 pdd14 ae8 md36 ac12 nmi a3 pdd15 ac6 md37 ad11 oc0# l1 pddak# ab5 md38 ab12 oc1# m4 pddrq af5 md39 ad13 osc ab4 pdior# af6 md40 ab14 par b12 pdiow# ab7 md41 ac13 pciclk a15 pgnt0# e15 md42 ad12 pcirst# e12 pgnt1# c16 md43 ac14 pcistp# e4 pgnt2# d14 md44 ab15 pcs0# / gpio19 n4 pgnt3# / gpio30 b5 md45 ab16 pcs1# / gpio16 p3 piordy aa5 md46 ac15 pda0 af8 pirqa# d5 md47 ad17 pda1 aa6 pirqb# e5 md48 ae23 pda2 ad7 pirqc# / gpio22 c6 md49 ae24 pdcs1# ab6 pirqd# / gpio23 e6 md50 af23 pdcs3# ac5 plock# f8 md51 af24 pdd0 aa7 pme# / gpio0 f1 md52 ae25 pdd1 ae6 preq0# d15 md53 ad23 pdd2 ad5 preq1# a14 md54 ae26 pdd3 ad8 preq2# e14 md55 af25 pdd4 ae5 preq3# / gpio29 a4 md56 ab26 pdd5 ac7 pwrbtn# h2 pwrok m2 sa18 u5 usbprt0+ j1
82443MX pciset 159 signal name pin signal name pin signal name pin rcin# d4 scas# af18 usbprt1- l2 refvcc f7 sd0 v5 usbprt1+ k2 reqa# / gpio2 d6 sd1 v2 vcc c3 ri# / gpio12 j4 sd2 t2 vcc ad3 rs0# w26 sd3 r2 vcc g6 rs1# v24 sd4 v6 vcc y6 rs2# v21 sd5 v4 vcc e11 rsmrst# m5 sd6 t3 vcc l11 rstdrv t4 sd7 t1 vcc n11 rtcx1 m1 serirq / gpio7 f6 vcc p11 rtcx2 m3 serr# d8 vcc t11 sa0 ac1 smbclk j3 vcc l13 sa1 ae1 smbdata j2 vcc t13 sa2 ad1 smi# c2 vcc ab13 sa3 ae2 spkr / gpio14 p1 vcc l14 sa4 aa2 sras# ae16 vcc t14 sa5 ab2 stop# f9 vcc l16 sa6 aa3 stpclk# e3 vcc n16 sa7 ac4 sus_stat# l3 vcc p16 sa8 ab3 susa# g3 vcc t16 sa9 w1 susb# g2 vcc aa17 sa10 aa1 susc# g1 vcc g21 sa11 ac2 susclk h1 vcc aa21 sa12 w5 sysclk v3 vcc ad24 sa13 ac3 tc ad4 vccrtc n2 sa14 w2 test# k5 vccsus k6 sa15 y1 thrm# / gpio8 h6 vccusb l5 sa16 u6 trdy# f10 vss c19 sa17 w4 usbprt0- l4 vss aa20 vss a1 vss m13 vss f21
82443MX pciset 160 signal name pin signal name pin signal name pin vss af1 vss n13 vss c22 vss f3 vss p13 vss ad22 vss n3 vss r13 vss e24 vss w3 vss c14 vss h24 vss ad6 vss m14 vss k24 vss c7 vss p12 vss p14 vss ad10 vss r12 vss r14 vss m11 vss t12 vss p24 vss r11 vss n14 vss u24 vss l12 vss ad14 vss aa24 vss m12 vss l15 vss a26 vss n12 vss m15 vss af26 vss n15 vss m16 vtta k21 vss p15 vss r16 vttb f20 vss r15 vss ad18 we# aa19 vss t15 vssusb k1 zerows# / gpio21 p2
82443MX pciset 161 table 82. gpio pin list signal name pin signal name pin signal name pin gpio0 / pme# f1 gpio11 / batlow# h3 gpio22 / pirqc# c6 gpio1 f4 gpio12 / ri# j4 gpio23 / pirqd# e6 gpio2 / reqa# d6 gpio13 r3 gpio24 / exsmi# e2 gpio3 / gnta# c5 gpio14 / spkr p1 gpio25 / mccs# t5 gpio4 j5 gpio15 n5 gpio26 / kbccs# r5 gpio5 af4 gpio16 / pcs1# p3 gpio27 / dreq3 p5 gpio6 / irq8# h5 gpio17 k4 gpio28 / dack3# p4 gpio7 / serirq f6 gpio18 g4 gpio29 / preq3# a4 gpio8 / thrm# h6 gpio19 / pcs0# n4 gpio30 / pgnt3# b5 gpio9 j6 gpio20 k3 gpio10 / lid h4 gpio21 / zerows# p2


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